Merge branch 'multiplatform/platform-data' into next/multiplatform

* multiplatform/platform-data:
  ARM: spear: move platform_data definitions
  ARM: samsung: move platform_data definitions
  ARM: orion: move platform_data definitions
  ARM: nomadik: move platform_data definitions
  ARM: w90x900: move platform_data definitions
  ARM: vt8500: move platform_data definitions
  ARM: tegra: move sdhci platform_data definition
  ARM: sa1100: move platform_data definitions
  ARM: pxa: move platform_data definitions
  ARM: netx: move platform_data definitions
  ARM: msm: move platform_data definitions
  ARM: imx: move platform_data definitions
  ARM: ep93xx: move platform_data definitions
  ARM: davinci: move platform_data definitions
  ARM: at91: move platform_data definitions

Conflicts due to removed files:
	arch/arm/mach-tegra/board-harmony.c
	arch/arm/mach-tegra/board-trimslice.c

Conflicts due to code removal:
	arch/arm/mach-tegra/board-paz00.c

Context conflicts in:
	drivers/mmc/host/sdhci-tegra.c
	drivers/net/irda/pxaficp_ir.c

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2012-09-22 00:22:33 -07:00
397 changed files with 573 additions and 574 deletions

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@@ -0,0 +1,21 @@
#ifndef __MACH_SSI_H
#define __MACH_SSI_H
struct snd_ac97;
extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end;
extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer;
struct imx_ssi_platform_data {
unsigned int flags;
#define IMX_SSI_DMA (1 << 0)
#define IMX_SSI_USE_AC97 (1 << 1)
#define IMX_SSI_NET (1 << 2)
#define IMX_SSI_SYN (1 << 3)
#define IMX_SSI_USE_I2S_SLAVE (1 << 4)
void (*ac97_reset) (struct snd_ac97 *ac97);
void (*ac97_warm_reset)(struct snd_ac97 *ac97);
};
#endif /* __MACH_SSI_H */

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@@ -0,0 +1,7 @@
#ifndef __PLAT_AUDIO_H
#define __PLAT_AUDIO_H
struct kirkwood_asoc_platform_data {
int burst;
};
#endif

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@@ -0,0 +1,8 @@
#ifndef _INCLUDE_PALMASOC_H_
#define _INCLUDE_PALMASOC_H_
struct palm27x_asoc_info {
int jack_gpio;
};
#endif

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@@ -0,0 +1,59 @@
/* arch/arm/plat-samsung/include/plat/audio.h
*
* Copyright (c) 2009 Samsung Electronics Co. Ltd
* Author: Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* The machine init code calls s3c*_ac97_setup_gpio with
* one of these defines in order to select appropriate bank
* of GPIO for AC97 pins
*/
#define S3C64XX_AC97_GPD 0
#define S3C64XX_AC97_GPE 1
extern void s3c64xx_ac97_setup_gpio(int);
/*
* The machine init code calls s5p*_spdif_setup_gpio with
* one of these defines in order to select appropriate bank
* of GPIO for S/PDIF pins
*/
#define S5PC100_SPDIF_GPD 0
#define S5PC100_SPDIF_GPG3 1
extern void s5pc100_spdif_setup_gpio(int);
struct samsung_i2s {
/* If the Primary DAI has 5.1 Channels */
#define QUIRK_PRI_6CHAN (1 << 0)
/* If the I2S block has a Stereo Overlay Channel */
#define QUIRK_SEC_DAI (1 << 1)
/*
* If the I2S block has no internal prescalar or MUX (I2SMOD[10] bit)
* The Machine driver must provide suitably set clock to the I2S block.
*/
#define QUIRK_NO_MUXPSR (1 << 2)
#define QUIRK_NEED_RSTCLR (1 << 3)
/* Quirks of the I2S controller */
u32 quirks;
/*
* Array of clock names that can be used to generate I2S signals.
* Also corresponds to clocks of I2SMOD[10]
*/
const char **src_clk;
dma_addr_t idma_addr;
};
/**
* struct s3c_audio_pdata - common platform data for audio device drivers
* @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
*/
struct s3c_audio_pdata {
int (*cfg_gpio)(struct platform_device *);
union {
struct samsung_i2s i2s;
} type;
};

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/* arch/arm/plat-samsung/include/plat/audio-simtec.h
*
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Simtec Audio support.
*/
/**
* struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
* @use_mpllin: Select codec clock from MPLLin
* @output_cdclk: Need to output CDCLK to the codec
* @have_mic: Set if we have a MIC socket
* @have_lout: Set if we have a LineOut socket
* @amp_gpio: GPIO pin to enable the AMP
* @amp_gain: Option GPIO to control AMP gain
*/
struct s3c24xx_audio_simtec_pdata {
unsigned int use_mpllin:1;
unsigned int output_cdclk:1;
unsigned int have_mic:1;
unsigned int have_lout:1;
int amp_gpio;
int amp_gain[2];
void (*startup)(void);
};

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/*
* Generic PXA PATA driver
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_PATA_PXA_H__
#define __MACH_PATA_PXA_H__
struct pata_pxa_pdata {
/* PXA DMA DREQ<0:2> pin */
uint32_t dma_dreq;
/* Register shift */
uint32_t reg_shift;
/* IRQ flags */
uint32_t irq_flags;
};
#endif /* __MACH_PATA_PXA_H__ */

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/* linux/arch/arm/plat-samsung/include/plat/ata.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung CF-ATA platform_device info
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_ATA_H
#define __ASM_PLAT_ATA_H __FILE__
/**
* struct s3c_ide_platdata - S3C IDE driver platform data.
* @setup_gpio: Setup the external GPIO pins to the right state for data
* transfer in true-ide mode.
*/
struct s3c_ide_platdata {
void (*setup_gpio)(void);
};
/*
* s3c_ide_set_platdata() - Setup the platform specifc data for IDE driver.
* @pdata: Platform data for IDE driver.
*/
extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata);
/* architecture-specific IDE configuration */
extern void s3c64xx_ide_setup_gpio(void);
extern void s5pc100_ide_setup_gpio(void);
extern void s5pv210_ide_setup_gpio(void);
#endif /*__ASM_PLAT_ATA_H */

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@@ -1,7 +1,7 @@
#ifndef __LINUX_ATMEL_AES_H
#define __LINUX_ATMEL_AES_H
#include <mach/at_hdmac.h>
#include <linux/platform_data/dma-atmel.h>
/**
* struct aes_dma_data - DMA data for AES

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/*
* mx1_camera.h - i.MX1/i.MXL camera driver header file
*
* Copyright (c) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com>
*
* Based on PXA camera.h file:
* Copyright (C) 2003, Intel Corporation
* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CAMERA_H_
#define __ASM_ARCH_CAMERA_H_
#define MX1_CAMERA_DATA_HIGH 1
#define MX1_CAMERA_PCLK_RISING 2
#define MX1_CAMERA_VSYNC_HIGH 4
extern unsigned char mx1_camera_sof_fiq_start, mx1_camera_sof_fiq_end;
/**
* struct mx1_camera_pdata - i.MX1/i.MXL camera platform data
* @mclk_10khz: master clock frequency in 10kHz units
* @flags: MX1 camera platform flags
*/
struct mx1_camera_pdata {
unsigned long mclk_10khz;
unsigned long flags;
};
#endif /* __ASM_ARCH_CAMERA_H_ */

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/*
* mx2-cam.h - i.MX27/i.MX25 camera driver header file
*
* Copyright (C) 2003, Intel Corporation
* Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de>
* Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __MACH_MX2_CAM_H_
#define __MACH_MX2_CAM_H_
#define MX2_CAMERA_EXT_VSYNC (1 << 1)
#define MX2_CAMERA_CCIR (1 << 2)
#define MX2_CAMERA_CCIR_INTERLACE (1 << 3)
#define MX2_CAMERA_HSYNC_HIGH (1 << 4)
#define MX2_CAMERA_GATED_CLOCK (1 << 5)
#define MX2_CAMERA_INV_DATA (1 << 6)
#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7)
/**
* struct mx2_camera_platform_data - optional platform data for mx2_camera
* @flags: any combination of MX2_CAMERA_*
* @clk: clock rate of the csi block / 2
*/
struct mx2_camera_platform_data {
unsigned long flags;
unsigned long clk;
};
#endif /* __MACH_MX2_CAM_H_ */

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@@ -0,0 +1,48 @@
/*
* mx3_camera.h - i.MX3x camera driver header file
*
* Copyright (C) 2008, Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MX3_CAMERA_H_
#define _MX3_CAMERA_H_
#include <linux/device.h>
#define MX3_CAMERA_CLK_SRC 1
#define MX3_CAMERA_EXT_VSYNC 2
#define MX3_CAMERA_DP 4
#define MX3_CAMERA_PCP 8
#define MX3_CAMERA_HSP 0x10
#define MX3_CAMERA_VSP 0x20
#define MX3_CAMERA_DATAWIDTH_4 0x40
#define MX3_CAMERA_DATAWIDTH_8 0x80
#define MX3_CAMERA_DATAWIDTH_10 0x100
#define MX3_CAMERA_DATAWIDTH_15 0x200
#define MX3_CAMERA_DATAWIDTH_MASK (MX3_CAMERA_DATAWIDTH_4 | MX3_CAMERA_DATAWIDTH_8 | \
MX3_CAMERA_DATAWIDTH_10 | MX3_CAMERA_DATAWIDTH_15)
/**
* struct mx3_camera_pdata - i.MX3x camera platform data
* @flags: MX3_CAMERA_* flags
* @mclk_10khz: master clock frequency in 10kHz units
* @dma_dev: IPU DMA device to match against in channel allocation
*/
struct mx3_camera_pdata {
unsigned long flags;
unsigned long mclk_10khz;
struct device *dma_dev;
};
#endif

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@@ -0,0 +1,44 @@
/*
camera.h - PXA camera driver header file
Copyright (C) 2003, Intel Corporation
Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_CAMERA_H_
#define __ASM_ARCH_CAMERA_H_
#define PXA_CAMERA_MASTER 1
#define PXA_CAMERA_DATAWIDTH_4 2
#define PXA_CAMERA_DATAWIDTH_5 4
#define PXA_CAMERA_DATAWIDTH_8 8
#define PXA_CAMERA_DATAWIDTH_9 0x10
#define PXA_CAMERA_DATAWIDTH_10 0x20
#define PXA_CAMERA_PCLK_EN 0x40
#define PXA_CAMERA_MCLK_EN 0x80
#define PXA_CAMERA_PCP 0x100
#define PXA_CAMERA_HSP 0x200
#define PXA_CAMERA_VSP 0x400
struct pxacamera_platform_data {
unsigned long flags;
unsigned long mclk_10khz;
};
extern void pxa_set_camera_info(struct pxacamera_platform_data *);
#endif /* __ASM_ARCH_CAMERA_H_ */

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/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYPTO_UX500_H
#define _CRYPTO_UX500_H
#include <linux/dmaengine.h>
#include <plat/ste_dma40.h>
struct hash_platform_data {
void *mem_to_engine;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
};
struct cryp_platform_data {
struct stedma40_chan_cfg mem_to_engine;
struct stedma40_chan_cfg engine_to_mem;
};
#endif

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/*
* Header file for the Atmel AHB DMA Controller driver
*
* Copyright (C) 2008 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT_HDMAC_H
#define AT_HDMAC_H
#include <linux/dmaengine.h>
/**
* struct at_dma_platform_data - Controller configuration parameters
* @nr_channels: Number of channels supported by hardware (max 8)
* @cap_mask: dma_capability flags supported by the platform
*/
struct at_dma_platform_data {
unsigned int nr_channels;
dma_cap_mask_t cap_mask;
};
/**
* struct at_dma_slave - Controller-specific information about a slave
* @dma_dev: required DMA master device
* @cfg: Platform-specific initializer for the CFG register
*/
struct at_dma_slave {
struct device *dma_dev;
u32 cfg;
};
/* Platform-configurable bits in CFG */
#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
#define ATC_SRC_H2SEL_SW (0x0 << 9)
#define ATC_SRC_H2SEL_HW (0x1 << 9)
#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
#define ATC_DST_H2SEL_SW (0x0 << 13)
#define ATC_DST_H2SEL_HW (0x1 << 13)
#define ATC_SOD (0x1 << 16) /* Stop On Done */
#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
#endif /* AT_HDMAC_H */

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#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <linux/types.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
/*
* M2P channels.
*
* Note that these values are also directly used for setting the PPALLOC
* register.
*/
#define EP93XX_DMA_I2S1 0
#define EP93XX_DMA_I2S2 1
#define EP93XX_DMA_AAC1 2
#define EP93XX_DMA_AAC2 3
#define EP93XX_DMA_AAC3 4
#define EP93XX_DMA_I2S3 5
#define EP93XX_DMA_UART1 6
#define EP93XX_DMA_UART2 7
#define EP93XX_DMA_UART3 8
#define EP93XX_DMA_IRDA 9
/* M2M channels */
#define EP93XX_DMA_SSP 10
#define EP93XX_DMA_IDE 11
/**
* struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
* @port: peripheral which is requesting the channel
* @direction: TX/RX channel
* @name: optional name for the channel, this is displayed in /proc/interrupts
*
* This information is passed as private channel parameter in a filter
* function. Note that this is only needed for slave/cyclic channels. For
* memcpy channels %NULL data should be passed.
*/
struct ep93xx_dma_data {
int port;
enum dma_transfer_direction direction;
const char *name;
};
/**
* struct ep93xx_dma_chan_data - platform specific data for a DMA channel
* @name: name of the channel, used for getting the right clock for the channel
* @base: mapped registers
* @irq: interrupt number used by this channel
*/
struct ep93xx_dma_chan_data {
const char *name;
void __iomem *base;
int irq;
};
/**
* struct ep93xx_dma_platform_data - platform data for the dmaengine driver
* @channels: array of channels which are passed to the driver
* @num_channels: number of channels in the array
*
* This structure is passed to the DMA engine driver via platform data. For
* M2P channels, contract is that even channels are for TX and odd for RX.
* There is no requirement for the M2M channels.
*/
struct ep93xx_dma_platform_data {
struct ep93xx_dma_chan_data *channels;
size_t num_channels;
};
static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
{
return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
}
/**
* ep93xx_dma_chan_direction - returns direction the channel can be used
* @chan: channel
*
* This function can be used in filter functions to find out whether the
* channel supports given DMA direction. Only M2P channels have such
* limitation, for M2M channels the direction is configurable.
*/
static inline enum dma_transfer_direction
ep93xx_dma_chan_direction(struct dma_chan *chan)
{
if (!ep93xx_dma_chan_is_m2p(chan))
return DMA_NONE;
/* even channels are for TX, odd for RX */
return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
}
#endif /* __ASM_ARCH_DMA_H */

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#ifndef __MACH_MXC_SDMA_H__
#define __MACH_MXC_SDMA_H__
/**
* struct sdma_script_start_addrs - SDMA script start pointers
*
* start addresses of the different functions in the physical
* address space of the SDMA engine.
*/
struct sdma_script_start_addrs {
s32 ap_2_ap_addr;
s32 ap_2_bp_addr;
s32 ap_2_ap_fixed_addr;
s32 bp_2_ap_addr;
s32 loopback_on_dsp_side_addr;
s32 mcu_interrupt_only_addr;
s32 firi_2_per_addr;
s32 firi_2_mcu_addr;
s32 per_2_firi_addr;
s32 mcu_2_firi_addr;
s32 uart_2_per_addr;
s32 uart_2_mcu_addr;
s32 per_2_app_addr;
s32 mcu_2_app_addr;
s32 per_2_per_addr;
s32 uartsh_2_per_addr;
s32 uartsh_2_mcu_addr;
s32 per_2_shp_addr;
s32 mcu_2_shp_addr;
s32 ata_2_mcu_addr;
s32 mcu_2_ata_addr;
s32 app_2_per_addr;
s32 app_2_mcu_addr;
s32 shp_2_per_addr;
s32 shp_2_mcu_addr;
s32 mshc_2_mcu_addr;
s32 mcu_2_mshc_addr;
s32 spdif_2_mcu_addr;
s32 mcu_2_spdif_addr;
s32 asrc_2_mcu_addr;
s32 ext_mem_2_ipu_addr;
s32 descrambler_addr;
s32 dptc_dvfs_addr;
s32 utra_addr;
s32 ram_code_start_addr;
};
/**
* struct sdma_platform_data - platform specific data for SDMA engine
*
* @fw_name The firmware name
* @script_addrs SDMA scripts addresses in SDMA ROM
*/
struct sdma_platform_data {
char *fw_name;
struct sdma_script_start_addrs *script_addrs;
};
#endif /* __MACH_MXC_SDMA_H__ */

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/*
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_DMA_H__
#define __ASM_ARCH_MXC_DMA_H__
#include <linux/scatterlist.h>
#include <linux/device.h>
#include <linux/dmaengine.h>
/*
* This enumerates peripheral types. Used for SDMA.
*/
enum sdma_peripheral_type {
IMX_DMATYPE_SSI, /* MCU domain SSI */
IMX_DMATYPE_SSI_SP, /* Shared SSI */
IMX_DMATYPE_MMC, /* MMC */
IMX_DMATYPE_SDHC, /* SDHC */
IMX_DMATYPE_UART, /* MCU domain UART */
IMX_DMATYPE_UART_SP, /* Shared UART */
IMX_DMATYPE_FIRI, /* FIRI */
IMX_DMATYPE_CSPI, /* MCU domain CSPI */
IMX_DMATYPE_CSPI_SP, /* Shared CSPI */
IMX_DMATYPE_SIM, /* SIM */
IMX_DMATYPE_ATA, /* ATA */
IMX_DMATYPE_CCM, /* CCM */
IMX_DMATYPE_EXT, /* External peripheral */
IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */
IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */
IMX_DMATYPE_DSP, /* DSP */
IMX_DMATYPE_MEMORY, /* Memory */
IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
IMX_DMATYPE_SPDIF, /* SPDIF */
IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
IMX_DMATYPE_ASRC, /* ASRC */
IMX_DMATYPE_ESAI, /* ESAI */
};
enum imx_dma_prio {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 1,
DMA_PRIO_LOW = 2
};
struct imx_dma_data {
int dma_request; /* DMA request line */
enum sdma_peripheral_type peripheral_type;
int priority;
};
static inline int imx_dma_is_ipu(struct dma_chan *chan)
{
return !strcmp(dev_name(chan->device->dev), "ipu-core");
}
static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
{
return strstr(dev_name(chan->device->dev), "sdma") ||
!strcmp(dev_name(chan->device->dev), "imx-dma");
}
#endif

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/*
* linux/arch/arm/mach-mmp/include/mach/sram.h
*
* SRAM Memory Management
*
* Copyright (c) 2011 Marvell Semiconductors Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_SRAM_H
#define __ASM_ARCH_SRAM_H
#include <linux/genalloc.h>
/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
#define SRAM_GRANULARITY 512
enum sram_type {
MMP_SRAM_UNDEFINED = 0,
MMP_ASRAM,
MMP_ISRAM,
};
struct sram_platdata {
char *pool_name;
int granularity;
};
extern struct gen_pool *sram_get_gpool(char *pool_name);
#endif /* __ASM_ARCH_SRAM_H */

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/*
* arch/arm/plat-orion/include/plat/mv_xor.h
*
* Marvell XOR platform device data definition file.
*/
#ifndef __PLAT_MV_XOR_H
#define __PLAT_MV_XOR_H
#include <linux/dmaengine.h>
#include <linux/mbus.h>
#define MV_XOR_SHARED_NAME "mv_xor_shared"
#define MV_XOR_NAME "mv_xor"
struct mv_xor_platform_data {
struct platform_device *shared;
int hw_id;
dma_cap_mask_t cap_mask;
size_t pool_size;
};
#endif

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@@ -0,0 +1,27 @@
/*
* arch/arm/mach-netx/include/mach/eth.h
*
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef ASMARM_ARCH_ETH_H
#define ASMARM_ARCH_ETH_H
struct netxeth_platform_data {
unsigned int xcno; /* number of xmac/xpec engine this eth uses */
};
#endif

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@@ -0,0 +1,51 @@
/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
*
* Copyright 2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C - HWMon interface for ADC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_ADC_HWMON_H
#define __ASM_ARCH_ADC_HWMON_H __FILE__
/**
* s3c_hwmon_chcfg - channel configuration
* @name: The name to give this channel.
* @mult: Multiply the ADC value read by this.
* @div: Divide the value from the ADC by this.
*
* The value read from the ADC is converted to a value that
* hwmon expects (mV) by result = (value_read * @mult) / @div.
*/
struct s3c_hwmon_chcfg {
const char *name;
unsigned int mult;
unsigned int div;
};
/**
* s3c_hwmon_pdata - HWMON platform data
* @in: One configuration for each possible channel used.
*/
struct s3c_hwmon_pdata {
struct s3c_hwmon_chcfg *in[8];
};
/**
* s3c_hwmon_set_platdata - Set platform data for S3C HWMON device
* @pd: Platform data to register to device.
*
* Register the given platform data for use with the S3C HWMON device.
* The call will copy the platform data, so the board definitions can
* make the structure itself __initdata.
*/
extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd);
#endif /* __ASM_ARCH_ADC_HWMON_H */

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/*
* DaVinci I2C controller platform_device info
*
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_I2C_H
#define __ASM_ARCH_I2C_H
/* All frequencies are expressed in kHz */
struct davinci_i2c_platform_data {
unsigned int bus_freq; /* standard bus frequency (kHz) */
unsigned int bus_delay; /* post-transaction delay (usec) */
unsigned int sda_pin; /* GPIO pin ID to use for SDA */
unsigned int scl_pin; /* GPIO pin ID to use for SCL */
};
/* for board setup code */
void davinci_init_i2c(struct davinci_i2c_platform_data *);
#endif /* __ASM_ARCH_I2C_H */

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@@ -0,0 +1,21 @@
/*
* i2c.h - i.MX I2C driver header file
*
* Copyright (c) 2008, Darius Augulis <augulis.darius@gmail.com>
*
* This file is released under the GPLv2
*/
#ifndef __ASM_ARCH_I2C_H_
#define __ASM_ARCH_I2C_H_
/**
* struct imxi2c_platform_data - structure of platform data for MXC I2C driver
* @bitrate: Bus speed measured in Hz
*
**/
struct imxi2c_platform_data {
u32 bitrate;
};
#endif /* __ASM_ARCH_I2C_H_ */

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#ifndef __ASM_ARCH_NUC900_I2C_H
#define __ASM_ARCH_NUC900_I2C_H
struct nuc900_platform_i2c {
int bus_num;
unsigned long bus_freq;
};
#endif /* __ASM_ARCH_NUC900_I2C_H */

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/* arch/arm/plat-s3c/include/plat/iic.h
*
* Copyright 2004-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller platform_device info
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IIC_H
#define __ASM_ARCH_IIC_H __FILE__
#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
/**
* struct s3c2410_platform_i2c - Platform data for s3c I2C.
* @bus_num: The bus number to use (if possible).
* @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER).
* @slave_addr: The I2C address for the slave device (if enabled).
* @frequency: The desired frequency in Hz of the bus. This is
* guaranteed to not be exceeded. If the caller does
* not care, use zero and the driver will select a
* useful default.
* @sda_delay: The delay (in ns) applied to SDA edges.
* @cfg_gpio: A callback to configure the pins for I2C operation.
*/
struct s3c2410_platform_i2c {
int bus_num;
unsigned int flags;
unsigned int slave_addr;
unsigned long frequency;
unsigned int sda_delay;
void (*cfg_gpio)(struct platform_device *dev);
};
/**
* s3c_i2c0_set_platdata - set platform data for i2c0 device
* @i2c: The platform data to set, or NULL for default data.
*
* Register the given platform data for use with the i2c0 device. This
* call copies the platform data, so the caller can use __initdata for
* their copy.
*
* This call will set cfg_gpio if is null to the default platform
* implementation.
*
* Any user of s3c_device_i2c0 should call this, even if it is with
* NULL to ensure that the device is given the default platform data
* as the driver will no longer carry defaults.
*/
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c3_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c4_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
extern struct s3c2410_platform_i2c default_i2c_data;
#endif /* __ASM_ARCH_IIC_H */

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#ifndef ASMARM_ARCH_IRDA_H
#define ASMARM_ARCH_IRDA_H
/* board specific transceiver capabilities */
#define IR_OFF 1
#define IR_SIRMODE 2
#define IR_FIRMODE 4
struct pxaficp_platform_data {
int transceiver_cap;
void (*transceiver_mode)(struct device *dev, int mode);
int (*startup)(struct device *dev);
void (*shutdown)(struct device *dev);
int gpio_pwdown; /* powerdown GPIO for the IrDA chip */
bool gpio_pwdown_inverted; /* gpio_pwdown is inverted */
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
void pxa2xx_transceiver_mode(struct device *dev, int mode);
#endif
#endif

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#ifndef __ASM_ARCH_PXA930_ROTARY_H
#define __ASM_ARCH_PXA930_ROTARY_H
/* NOTE:
*
* rotary can be either interpreted as a ralative input event (e.g.
* REL_WHEEL or REL_HWHEEL) or a specific key event (e.g. UP/DOWN
* or LEFT/RIGHT), depending on if up_key & down_key are assigned
* or rel_code is assigned a non-zero value. When all are non-zero,
* up_key and down_key will be preferred.
*/
struct pxa930_rotary_platform_data {
int up_key;
int down_key;
int rel_code;
};
void __init pxa930_set_rotarykey_info(struct pxa930_rotary_platform_data *info);
#endif /* __ASM_ARCH_PXA930_ROTARY_H */

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/*
* Copyright (C) 2010 ST Microelectronics
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_KEYBOARD_H
#define __PLAT_KEYBOARD_H
#include <linux/bitops.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/types.h>
#define DECLARE_9x9_KEYMAP(_name) \
int _name[] = { \
KEY(0, 0, KEY_ESC), \
KEY(0, 1, KEY_1), \
KEY(0, 2, KEY_2), \
KEY(0, 3, KEY_3), \
KEY(0, 4, KEY_4), \
KEY(0, 5, KEY_5), \
KEY(0, 6, KEY_6), \
KEY(0, 7, KEY_7), \
KEY(0, 8, KEY_8), \
KEY(1, 0, KEY_9), \
KEY(1, 1, KEY_MINUS), \
KEY(1, 2, KEY_EQUAL), \
KEY(1, 3, KEY_BACKSPACE), \
KEY(1, 4, KEY_TAB), \
KEY(1, 5, KEY_Q), \
KEY(1, 6, KEY_W), \
KEY(1, 7, KEY_E), \
KEY(1, 8, KEY_R), \
KEY(2, 0, KEY_T), \
KEY(2, 1, KEY_Y), \
KEY(2, 2, KEY_U), \
KEY(2, 3, KEY_I), \
KEY(2, 4, KEY_O), \
KEY(2, 5, KEY_P), \
KEY(2, 6, KEY_LEFTBRACE), \
KEY(2, 7, KEY_RIGHTBRACE), \
KEY(2, 8, KEY_ENTER), \
KEY(3, 0, KEY_LEFTCTRL), \
KEY(3, 1, KEY_A), \
KEY(3, 2, KEY_S), \
KEY(3, 3, KEY_D), \
KEY(3, 4, KEY_F), \
KEY(3, 5, KEY_G), \
KEY(3, 6, KEY_H), \
KEY(3, 7, KEY_J), \
KEY(3, 8, KEY_K), \
KEY(4, 0, KEY_L), \
KEY(4, 1, KEY_SEMICOLON), \
KEY(4, 2, KEY_APOSTROPHE), \
KEY(4, 3, KEY_GRAVE), \
KEY(4, 4, KEY_LEFTSHIFT), \
KEY(4, 5, KEY_BACKSLASH), \
KEY(4, 6, KEY_Z), \
KEY(4, 7, KEY_X), \
KEY(4, 8, KEY_C), \
KEY(5, 0, KEY_V), \
KEY(5, 1, KEY_B), \
KEY(5, 2, KEY_N), \
KEY(5, 3, KEY_M), \
KEY(5, 4, KEY_COMMA), \
KEY(5, 5, KEY_DOT), \
KEY(5, 6, KEY_SLASH), \
KEY(5, 7, KEY_RIGHTSHIFT), \
KEY(5, 8, KEY_KPASTERISK), \
KEY(6, 0, KEY_LEFTALT), \
KEY(6, 1, KEY_SPACE), \
KEY(6, 2, KEY_CAPSLOCK), \
KEY(6, 3, KEY_F1), \
KEY(6, 4, KEY_F2), \
KEY(6, 5, KEY_F3), \
KEY(6, 6, KEY_F4), \
KEY(6, 7, KEY_F5), \
KEY(6, 8, KEY_F6), \
KEY(7, 0, KEY_F7), \
KEY(7, 1, KEY_F8), \
KEY(7, 2, KEY_F9), \
KEY(7, 3, KEY_F10), \
KEY(7, 4, KEY_NUMLOCK), \
KEY(7, 5, KEY_SCROLLLOCK), \
KEY(7, 6, KEY_KP7), \
KEY(7, 7, KEY_KP8), \
KEY(7, 8, KEY_KP9), \
KEY(8, 0, KEY_KPMINUS), \
KEY(8, 1, KEY_KP4), \
KEY(8, 2, KEY_KP5), \
KEY(8, 3, KEY_KP6), \
KEY(8, 4, KEY_KPPLUS), \
KEY(8, 5, KEY_KP1), \
KEY(8, 6, KEY_KP2), \
KEY(8, 7, KEY_KP3), \
KEY(8, 8, KEY_KP0), \
}
#define DECLARE_6x6_KEYMAP(_name) \
int _name[] = { \
KEY(0, 0, KEY_RESERVED), \
KEY(0, 1, KEY_1), \
KEY(0, 2, KEY_2), \
KEY(0, 3, KEY_3), \
KEY(0, 4, KEY_4), \
KEY(0, 5, KEY_5), \
KEY(1, 0, KEY_Q), \
KEY(1, 1, KEY_W), \
KEY(1, 2, KEY_E), \
KEY(1, 3, KEY_R), \
KEY(1, 4, KEY_T), \
KEY(1, 5, KEY_Y), \
KEY(2, 0, KEY_D), \
KEY(2, 1, KEY_F), \
KEY(2, 2, KEY_G), \
KEY(2, 3, KEY_H), \
KEY(2, 4, KEY_J), \
KEY(2, 5, KEY_K), \
KEY(3, 0, KEY_B), \
KEY(3, 1, KEY_N), \
KEY(3, 2, KEY_M), \
KEY(3, 3, KEY_COMMA), \
KEY(3, 4, KEY_DOT), \
KEY(3, 5, KEY_SLASH), \
KEY(4, 0, KEY_F6), \
KEY(4, 1, KEY_F7), \
KEY(4, 2, KEY_F8), \
KEY(4, 3, KEY_F9), \
KEY(4, 4, KEY_F10), \
KEY(4, 5, KEY_NUMLOCK), \
KEY(5, 0, KEY_KP2), \
KEY(5, 1, KEY_KP3), \
KEY(5, 2, KEY_KP0), \
KEY(5, 3, KEY_KPDOT), \
KEY(5, 4, KEY_RO), \
KEY(5, 5, KEY_ZENKAKUHANKAKU), \
}
#define KEYPAD_9x9 0
#define KEYPAD_6x6 1
#define KEYPAD_2x2 2
/**
* struct kbd_platform_data - spear keyboard platform data
* keymap: pointer to keymap data (table and size)
* rep: enables key autorepeat
* mode: choose keyboard support(9x9, 6x6, 2x2)
* suspended_rate: rate at which keyboard would operate in suspended mode
*
* This structure is supposed to be used by platform code to supply
* keymaps to drivers that implement keyboards.
*/
struct kbd_platform_data {
const struct matrix_keymap_data *keymap;
bool rep;
unsigned int mode;
unsigned int suspended_rate;
};
#endif /* __PLAT_KEYBOARD_H */

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/*
* arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
*/
#ifndef __ASM_ARCH_EP93XX_KEYPAD_H
#define __ASM_ARCH_EP93XX_KEYPAD_H
struct matrix_keymap_data;
/* flags for the ep93xx_keypad driver */
#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */
#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */
#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */
#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */
#define EP93XX_KEYPAD_KDIV (1<<4) /* 1/4 clock or 1/16 clock */
#define EP93XX_KEYPAD_AUTOREPEAT (1<<5) /* enable key autorepeat */
/**
* struct ep93xx_keypad_platform_data - platform specific device structure
* @keymap_data: pointer to &matrix_keymap_data
* @debounce: debounce start count; terminal count is 0xff
* @prescale: row/column counter pre-scaler load value
* @flags: see above
*/
struct ep93xx_keypad_platform_data {
struct matrix_keymap_data *keymap_data;
unsigned int debounce;
unsigned int prescale;
unsigned int flags;
};
#define EP93XX_MATRIX_ROWS (8)
#define EP93XX_MATRIX_COLS (8)
#endif /* __ASM_ARCH_EP93XX_KEYPAD_H */

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@@ -0,0 +1,50 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Author: Naveen Kumar Gaddipati <naveen.gaddipati@stericsson.com>
*
* ux500 Scroll key and Keypad Encoder (SKE) header
*/
#ifndef __SKE_H
#define __SKE_H
#include <linux/input/matrix_keypad.h>
/* register definitions for SKE peripheral */
#define SKE_CR 0x00
#define SKE_VAL0 0x04
#define SKE_VAL1 0x08
#define SKE_DBCR 0x0C
#define SKE_IMSC 0x10
#define SKE_RIS 0x14
#define SKE_MIS 0x18
#define SKE_ICR 0x1C
/*
* Keypad module
*/
/**
* struct keypad_platform_data - structure for platform specific data
* @init: pointer to keypad init function
* @exit: pointer to keypad deinitialisation function
* @keymap_data: matrix scan code table for keycodes
* @krow: maximum number of rows
* @kcol: maximum number of columns
* @debounce_ms: platform specific debounce time
* @no_autorepeat: flag for auto repetition
* @wakeup_enable: allow waking up the system
*/
struct ske_keypad_platform_data {
int (*init)(void);
int (*exit)(void);
const struct matrix_keymap_data *keymap_data;
u8 krow;
u8 kcol;
u8 debounce_ms;
bool no_autorepeat;
bool wakeup_enable;
};
#endif /*__SKE_KPD_H*/

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#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
#define __ASM_ARCH_PXA27x_KEYPAD_H
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#define MAX_MATRIX_KEY_ROWS (8)
#define MAX_MATRIX_KEY_COLS (8)
#define MATRIX_ROW_SHIFT (3)
#define MAX_DIRECT_KEY_NUM (8)
/* pxa3xx keypad platform specific parameters
*
* NOTE:
* 1. direct_key_num indicates the number of keys in the direct keypad
* _plus_ the number of rotary-encoder sensor inputs, this can be
* left as 0 if only rotary encoders are enabled, the driver will
* automatically calculate this
*
* 2. direct_key_map is the key code map for the direct keys, if rotary
* encoder(s) are enabled, direct key 0/1(2/3) will be ignored
*
* 3. rotary can be either interpreted as a relative input event (e.g.
* REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
*
* 4. matrix key and direct key will use the same debounce_interval by
* default, which should be sufficient in most cases
*
* pxa168 keypad platform specific parameter
*
* NOTE:
* clear_wakeup_event callback is a workaround required to clear the
* keypad interrupt. The keypad wake must be cleared in addition to
* reading the MI/DI bits in the KPC register.
*/
struct pxa27x_keypad_platform_data {
/* code map for the matrix keys */
unsigned int matrix_key_rows;
unsigned int matrix_key_cols;
unsigned int *matrix_key_map;
int matrix_key_map_size;
/* direct keys */
int direct_key_num;
unsigned int direct_key_map[MAX_DIRECT_KEY_NUM];
/* the key output may be low active */
int direct_key_low_active;
/* give board a chance to choose the start direct key */
unsigned int direct_key_mask;
/* rotary encoders 0 */
int enable_rotary0;
int rotary0_rel_code;
int rotary0_up_key;
int rotary0_down_key;
/* rotary encoders 1 */
int enable_rotary1;
int rotary1_rel_code;
int rotary1_up_key;
int rotary1_down_key;
/* key debounce interval */
unsigned int debounce_interval;
/* clear wakeup event requirement for pxa168 */
void (*clear_wakeup_event)(void);
};
extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */

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#ifndef __ASM_ARCH_W90P910_KEYPAD_H
#define __ASM_ARCH_W90P910_KEYPAD_H
#include <linux/input/matrix_keypad.h>
extern void mfp_set_groupi(struct device *dev);
struct w90p910_keypad_platform_data {
const struct matrix_keymap_data *keymap_data;
unsigned int prescale;
unsigned int debounce;
};
#endif /* __ASM_ARCH_W90P910_KEYPAD_H */

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@@ -0,0 +1,42 @@
/*
* Copyright (C) 2009 Texas Instruments, Inc
*
* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef DAVINCI_KEYSCAN_H
#define DAVINCI_KEYSCAN_H
#include <linux/io.h>
enum davinci_matrix_types {
DAVINCI_KEYSCAN_MATRIX_4X4,
DAVINCI_KEYSCAN_MATRIX_5X3,
};
struct davinci_ks_platform_data {
int (*device_enable)(struct device *dev);
unsigned short *keymap;
u32 keymapsize;
u8 rep:1;
u8 strobe;
u8 interval;
u8 matrix_type;
};
#endif

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/*
* arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
*
* Platform data structure for netxbig LED driver
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_LEDS_NETXBIG_H
#define __MACH_LEDS_NETXBIG_H
struct netxbig_gpio_ext {
unsigned *addr;
int num_addr;
unsigned *data;
int num_data;
unsigned enable;
};
enum netxbig_led_mode {
NETXBIG_LED_OFF,
NETXBIG_LED_ON,
NETXBIG_LED_SATA,
NETXBIG_LED_TIMER1,
NETXBIG_LED_TIMER2,
NETXBIG_LED_MODE_NUM,
};
#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
struct netxbig_led_timer {
unsigned long delay_on;
unsigned long delay_off;
enum netxbig_led_mode mode;
};
struct netxbig_led {
const char *name;
const char *default_trigger;
int mode_addr;
int *mode_val;
int bright_addr;
};
struct netxbig_led_platform_data {
struct netxbig_gpio_ext *gpio_ext;
struct netxbig_led_timer *timer;
int num_timer;
struct netxbig_led *leds;
int num_leds;
};
#endif /* __MACH_LEDS_NETXBIG_H */

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/*
* arch/arm/mach-kirkwood/include/mach/leds-ns2.h
*
* Platform data structure for Network Space v2 LED driver
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_LEDS_NS2_H
#define __MACH_LEDS_NS2_H
struct ns2_led {
const char *name;
const char *default_trigger;
unsigned cmd;
unsigned slow;
};
struct ns2_led_platform_data {
int num_leds;
struct ns2_led *leds;
};
#endif /* __MACH_LEDS_NS2_H */

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/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h
*
* Copyright (c) 2006 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX - LEDs GPIO connector
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_LEDSGPIO_H
#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h"
#define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */
#define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */
struct s3c24xx_led_platdata {
unsigned int gpio;
unsigned int flags;
char *name;
char *def_trigger;
};
#endif /* __ASM_ARCH_LEDSGPIO_H */

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/*
* arch/arm/mach-sa1100/include/mach/mcp.h
*
* Copyright (C) 2005 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_MCP_H
#define __ASM_ARM_ARCH_MCP_H
#include <linux/types.h>
struct mcp_plat_data {
u32 mccr0;
u32 mccr1;
unsigned int sclk_rate;
void *codec_pdata;
};
#endif

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/*
* Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
*
* S5P series MIPI CSI slave device support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_
#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__
struct platform_device;
/**
* struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
* @clk_rate: bus clock frequency
* @lanes: number of data lanes used
* @alignment: data alignment in bits
* @hs_settle: HS-RX settle time
* @fixed_phy_vdd: false to enable external D-PHY regulator management in the
* driver or true in case this regulator has no enable function
* @phy_enable: pointer to a callback controlling D-PHY enable/reset
*/
struct s5p_platform_mipi_csis {
unsigned long clk_rate;
u8 lanes;
u8 alignment;
u8 hs_settle;
bool fixed_phy_vdd;
int (*phy_enable)(struct platform_device *pdev, bool on);
};
/**
* s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
* @pdev: MIPI-CSIS platform device
* @on: true to enable D-PHY and deassert its reset
* false to disable D-PHY
*/
int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */

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/*
* Board-specific MMC configuration
*/
#ifndef _DAVINCI_MMC_H
#define _DAVINCI_MMC_H
#include <linux/types.h>
#include <linux/mmc/host.h>
struct davinci_mmc_config {
/* get_cd()/get_wp() may sleep */
int (*get_cd)(int module);
int (*get_ro)(int module);
void (*set_power)(int module, bool on);
/* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
u8 wires;
u32 max_freq;
/* any additional host capabilities: OR'd in to mmc->f_caps */
u32 caps;
/* Version of the MMC/SD controller */
u8 version;
/* Number of sg segments */
u8 nr_sg;
};
void davinci_setup_mmc(int module, struct davinci_mmc_config *config);
enum {
MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
MMC_CTLR_VERSION_2, /* DA830 */
};
#endif

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/*
* Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#ifndef __ASM_ARCH_IMX_ESDHC_H
#define __ASM_ARCH_IMX_ESDHC_H
enum wp_types {
ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
ESDHC_WP_GPIO, /* external gpio pin for WP */
};
enum cd_types {
ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
ESDHC_CD_GPIO, /* external gpio pin for CD */
ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */
};
/**
* struct esdhc_platform_data - platform data for esdhc on i.MX
*
* ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
*
* @wp_gpio: gpio for write_protect
* @cd_gpio: gpio for card_detect interrupt
* @wp_type: type of write_protect method (see wp_types enum above)
* @cd_type: type of card_detect method (see cd_types enum above)
*/
struct esdhc_platform_data {
unsigned int wp_gpio;
unsigned int cd_gpio;
enum wp_types wp_type;
enum cd_types cd_type;
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */

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/*
* arch/arm/include/asm/mach/mmc.h
*/
#ifndef ASMARM_MACH_MMC_H
#define ASMARM_MACH_MMC_H
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <linux/mmc/sdio_func.h>
struct msm_mmc_gpio {
unsigned no;
const char *name;
};
struct msm_mmc_gpio_data {
struct msm_mmc_gpio *gpio;
u8 size;
};
struct msm_mmc_platform_data {
unsigned int ocr_mask; /* available voltages */
u32 (*translate_vdd)(struct device *, unsigned int);
unsigned int (*status)(struct device *);
int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
struct msm_mmc_gpio_data *gpio_data;
void (*init_card)(struct mmc_card *card);
};
#endif

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/*
* arch/arm/plat-orion/include/plat/mvsdio.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_MVSDIO_H
#define __MACH_MVSDIO_H
#include <linux/mbus.h>
struct mvsdio_platform_data {
unsigned int clock;
int gpio_card_detect;
int gpio_write_protect;
};
#endif

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#ifndef ASMARM_ARCH_MMC_H
#define ASMARM_ARCH_MMC_H
#include <linux/mmc/host.h>
struct device;
/* board specific SDHC data, optional.
* If not present, a writable card with 3,3V is assumed.
*/
struct imxmmc_platform_data {
/* Return values for the get_ro callback should be:
* 0 for a read/write card
* 1 for a read-only card
* -ENOSYS when not supported (equal to NULL callback)
* or a negative errno value when something bad happened
*/
int (*get_ro)(struct device *);
/* board specific hook to (de)initialize the SD slot.
* The board code can call 'handler' on a card detection
* change giving data as argument.
*/
int (*init)(struct device *dev, irq_handler_t handler, void *data);
void (*exit)(struct device *dev, void *data);
/* available voltages. If not given, assume
* MMC_VDD_32_33 | MMC_VDD_33_34
*/
unsigned int ocr_avail;
/* adjust slot voltage */
void (*setpower)(struct device *, unsigned int vdd);
/* enable card detect using DAT3 */
int dat3_card_detect;
};
#endif

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#ifndef ASMARM_ARCH_MMC_H
#define ASMARM_ARCH_MMC_H
#include <linux/mmc/host.h>
#include <linux/interrupt.h>
struct device;
struct mmc_host;
struct pxamci_platform_data {
unsigned int ocr_mask; /* available voltages */
unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
int (*init)(struct device *, irq_handler_t , void *);
int (*get_ro)(struct device *);
void (*setpower)(struct device *, unsigned int);
void (*exit)(struct device *, void *);
int gpio_card_detect; /* gpio detecting card insertion */
int gpio_card_ro; /* gpio detecting read only toggle */
bool gpio_card_ro_invert; /* gpio ro is inverted */
int gpio_power; /* gpio powering up MMC bus */
bool gpio_power_invert; /* gpio power is inverted */
};
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
#endif

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#ifndef _ARCH_MCI_H
#define _ARCH_MCI_H
/**
* struct s3c24xx_mci_pdata - sd/mmc controller platform data
* @no_wprotect: Set this to indicate there is no write-protect switch.
* @no_detect: Set this if there is no detect switch.
* @wprotect_invert: Invert the default sense of the write protect switch.
* @detect_invert: Invert the default sense of the write protect switch.
* @use_dma: Set to allow the use of DMA.
* @gpio_detect: GPIO number for the card detect line.
* @gpio_wprotect: GPIO number for the write protect line.
* @ocr_avail: The mask of the available power states, non-zero to use.
* @set_power: Callback to control the power mode.
*
* The @gpio_detect is used for card detection when @no_wprotect is unset,
* and the default sense is that 0 returned from gpio_get_value() means
* that a card is inserted. If @detect_invert is set, then the value from
* gpio_get_value() is inverted, which makes 1 mean card inserted.
*
* The driver will use @gpio_wprotect to signal whether the card is write
* protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
* means the card is read/write, and 1 means read-only. The @wprotect_invert
* will invert the value returned from gpio_get_value().
*
* Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
* to a non-zero value, otherwise the default of 3.2-3.4V is used.
*/
struct s3c24xx_mci_pdata {
unsigned int no_wprotect:1;
unsigned int no_detect:1;
unsigned int wprotect_invert:1;
unsigned int detect_invert:1; /* set => detect active high */
unsigned int use_dma:1;
unsigned int gpio_detect;
unsigned int gpio_wprotect;
unsigned long ocr_avail;
void (*set_power)(unsigned char power_mode,
unsigned short vdd);
};
/**
* s3c24xx_mci_set_platdata - set platform data for mmc/sdi device
* @pdata: The platform data
*
* Copy the platform data supplied by @pdata so that this can be marked
* __initdata.
*/
extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata);
#endif /* _ARCH_NCI_H */

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/*
* Copyright (C) 2009 Palm, Inc.
* Author: Yvonne Yip <y@palm.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __PLATFORM_DATA_TEGRA_SDHCI_H
#define __PLATFORM_DATA_TEGRA_SDHCI_H
#include <linux/mmc/host.h>
struct tegra_sdhci_platform_data {
int cd_gpio;
int wp_gpio;
int power_gpio;
int is_8bit;
int pm_flags;
};
#endif

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#ifndef __ASM_ARCH_PXA930_TRKBALL_H
#define __ASM_ARCH_PXA930_TRKBALL_H
struct pxa930_trkball_platform_data {
int x_filter;
int y_filter;
};
#endif /* __ASM_ARCH_PXA930_TRKBALL_H */

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/*
* TI DaVinci AEMIF support
*
* Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef _MACH_DAVINCI_AEMIF_H
#define _MACH_DAVINCI_AEMIF_H
#define NRCSR_OFFSET 0x00
#define AWCCR_OFFSET 0x04
#define A1CR_OFFSET 0x10
#define ACR_ASIZE_MASK 0x3
#define ACR_EW_MASK BIT(30)
#define ACR_SS_MASK BIT(31)
/* All timings in nanoseconds */
struct davinci_aemif_timing {
u8 wsetup;
u8 wstrobe;
u8 whold;
u8 rsetup;
u8 rstrobe;
u8 rhold;
u8 ta;
};
int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
void __iomem *base, unsigned cs);
#endif

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/*
* mach-davinci/nand.h
*
* Copyright © 2006 Texas Instruments.
*
* Ported to 2.6.23 Copyright © 2008 by
* Sander Huijsen <Shuijsen@optelecom-nkf.com>
* Troy Kisky <troy.kisky@boundarydevices.com>
* Dirk Behme <Dirk.Behme@gmail.com>
*
* --------------------------------------------------------------------------
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ARCH_ARM_DAVINCI_NAND_H
#define __ARCH_ARM_DAVINCI_NAND_H
#include <linux/mtd/nand.h>
#define NANDFCR_OFFSET 0x60
#define NANDFSR_OFFSET 0x64
#define NANDF1ECC_OFFSET 0x70
/* 4-bit ECC syndrome registers */
#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
#define NAND_4BIT_ECC1_OFFSET 0xc0
#define NAND_4BIT_ECC2_OFFSET 0xc4
#define NAND_4BIT_ECC3_OFFSET 0xc8
#define NAND_4BIT_ECC4_OFFSET 0xcc
#define NAND_ERR_ADD1_OFFSET 0xd0
#define NAND_ERR_ADD2_OFFSET 0xd4
#define NAND_ERR_ERRVAL1_OFFSET 0xd8
#define NAND_ERR_ERRVAL2_OFFSET 0xdc
/* NOTE: boards don't need to use these address bits
* for ALE/CLE unless they support booting from NAND.
* They're used unless platform data overrides them.
*/
#define MASK_ALE 0x08
#define MASK_CLE 0x10
struct davinci_nand_pdata { /* platform_data */
uint32_t mask_ale;
uint32_t mask_cle;
/* for packages using two chipselects */
uint32_t mask_chipsel;
/* board's default static partition info */
struct mtd_partition *parts;
unsigned nr_parts;
/* none == NAND_ECC_NONE (strongly *not* advised!!)
* soft == NAND_ECC_SOFT
* else == NAND_ECC_HW, according to ecc_bits
*
* All DaVinci-family chips support 1-bit hardware ECC.
* Newer ones also support 4-bit ECC, but are awkward
* using it with large page chips.
*/
nand_ecc_modes_t ecc_mode;
u8 ecc_bits;
/* e.g. NAND_BUSWIDTH_16 */
unsigned options;
/* e.g. NAND_BBT_USE_FLASH */
unsigned bbt_options;
/* Main and mirror bbt descriptor overrides */
struct nand_bbt_descr *bbt_td;
struct nand_bbt_descr *bbt_md;
/* Access timings */
struct davinci_aemif_timing *timing;
};
#endif /* __ARCH_ARM_DAVINCI_NAND_H */

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_NAND_H
#define __ASM_ARCH_NAND_H
#include <linux/mtd/partitions.h>
struct mxc_nand_platform_data {
unsigned int width; /* data bus width in bytes */
unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */
unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
struct mtd_partition *parts; /* partition table */
int nr_parts; /* size of parts */
};
#endif /* __ASM_ARCH_NAND_H */

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#ifndef __ASM_ARCH_PXA3XX_NAND_H
#define __ASM_ARCH_PXA3XX_NAND_H
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
struct pxa3xx_nand_timing {
unsigned int tCH; /* Enable signal hold time */
unsigned int tCS; /* Enable signal setup time */
unsigned int tWH; /* ND_nWE high duration */
unsigned int tWP; /* ND_nWE pulse time */
unsigned int tRH; /* ND_nRE high duration */
unsigned int tRP; /* ND_nRE pulse width */
unsigned int tR; /* ND_nWE high to ND_nRE low for read */
unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
};
struct pxa3xx_nand_cmdset {
uint16_t read1;
uint16_t read2;
uint16_t program;
uint16_t read_status;
uint16_t read_id;
uint16_t erase;
uint16_t reset;
uint16_t lock;
uint16_t unlock;
uint16_t lock_status;
};
struct pxa3xx_nand_flash {
char *name;
uint32_t chip_id;
unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
unsigned int num_blocks; /* Number of physical blocks in Flash */
struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
};
/*
* Current pxa3xx_nand controller has two chip select which
* both be workable.
*
* Notice should be taken that:
* When you want to use this feature, you should not enable the
* keep configuration feature, for two chip select could be
* attached with different nand chip. The different page size
* and timing requirement make the keep configuration impossible.
*/
/* The max num of chip select current support */
#define NUM_CHIP_SELECT (2)
struct pxa3xx_nand_platform_data {
/* the data flash bus is shared between the Static Memory
* Controller and the Data Flash Controller, the arbiter
* controls the ownership of the bus
*/
int enable_arbiter;
/* allow platform code to keep OBM/bootloader defined NFC config */
int keep_config;
/* indicate how many chip selects will be used */
int num_cs;
const struct mtd_partition *parts[NUM_CHIP_SELECT];
unsigned int nr_parts[NUM_CHIP_SELECT];
const struct pxa3xx_nand_flash * flash;
size_t num_flash;
};
extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
#endif /* __ASM_ARCH_PXA3XX_NAND_H */

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/* arch/arm/mach-s3c2410/include/mach/nand.h
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - NAND device controller platform_device info
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/**
* struct s3c2410_nand_set - define a set of one or more nand chips
* @disable_ecc: Entirely disable ECC - Dangerous
* @flash_bbt: Openmoko u-boot can create a Bad Block Table
* Setting this flag will allow the kernel to
* look for it at boot time and also skip the NAND
* scan.
* @options: Default value to set into 'struct nand_chip' options.
* @nr_chips: Number of chips in this set
* @nr_partitions: Number of partitions pointed to by @partitions
* @name: Name of set (optional)
* @nr_map: Map for low-layer logical to physical chip numbers (option)
* @partitions: The mtd partition list
*
* define a set of one or more nand chips registered with an unique mtd. Also
* allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
* a warning at boot time.
*/
struct s3c2410_nand_set {
unsigned int disable_ecc:1;
unsigned int flash_bbt:1;
unsigned int options;
int nr_chips;
int nr_partitions;
char *name;
int *nr_map;
struct mtd_partition *partitions;
struct nand_ecclayout *ecc_layout;
};
struct s3c2410_platform_nand {
/* timing information for controller, all times in nanoseconds */
int tacls; /* time for active CLE/ALE to nWE/nOE */
int twrph0; /* active time for nWE/nOE */
int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
unsigned int ignore_unset_ecc:1;
int nr_sets;
struct s3c2410_nand_set *sets;
void (*select_chip)(struct s3c2410_nand_set *,
int chip);
};
/**
* s3c_nand_set_platdata() - register NAND platform data.
* @nand: The NAND platform data to register with s3c_device_nand.
*
* This function copies the given NAND platform data, @nand and registers
* it with the s3c_device_nand. This allows @nand to be __initdata.
*/
extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);

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@@ -0,0 +1,16 @@
#ifndef __ASM_ARCH_NAND_H
#define __ASM_ARCH_NAND_H
struct nomadik_nand_platform_data {
struct mtd_partition *parts;
int nparts;
int options;
int (*init) (void);
int (*exit) (void);
};
#define NAND_IO_DATA 0x40000000
#define NAND_IO_CMD 0x40800000
#define NAND_IO_ADDR 0x41000000
#endif /* __ASM_ARCH_NAND_H */

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/*
* arch/arm/plat-orion/include/plat/orion_nand.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_ORION_NAND_H
#define __PLAT_ORION_NAND_H
/*
* Device bus NAND private data
*/
struct orion_nand_data {
struct mtd_partition *parts;
int (*dev_ready)(struct mtd_info *mtd);
u32 nr_parts;
u8 ale; /* address line number connected to ALE */
u8 cle; /* address line number connected to CLE */
u8 width; /* buswidth */
u8 chip_delay;
};
#endif

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#ifndef __ARCOM_PCMCIA_H
#define __ARCOM_PCMCIA_H
struct arcom_pcmcia_pdata {
int cd_gpio;
int rdy_gpio;
int pwr_gpio;
void (*reset)(int state);
};
#endif

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@@ -0,0 +1,35 @@
/*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef ASMARM_ARCH_UART_H
#define ASMARM_ARCH_UART_H
#define IMXUART_HAVE_RTSCTS (1<<0)
#define IMXUART_IRDA (1<<1)
struct imxuart_platform_data {
int (*init)(struct platform_device *pdev);
void (*exit)(struct platform_device *pdev);
unsigned int flags;
void (*irda_enable)(int enable);
unsigned int irda_inv_rx:1;
unsigned int irda_inv_tx:1;
unsigned short transceiver_delay;
};
#endif

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@@ -0,0 +1,89 @@
/*
* Copyright 2009 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ARCH_ARM_DAVINCI_SPI_H
#define __ARCH_ARM_DAVINCI_SPI_H
#include <mach/edma.h>
#define SPI_INTERN_CS 0xFF
enum {
SPI_VERSION_1, /* For DM355/DM365/DM6467 */
SPI_VERSION_2, /* For DA8xx */
};
/**
* davinci_spi_platform_data - Platform data for SPI master device on DaVinci
*
* @version: version of the SPI IP. Different DaVinci devices have slightly
* varying versions of the same IP.
* @num_chipselect: number of chipselects supported by this SPI master
* @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt
* controller withn the SoC. Possible values are 0 and 1.
* @chip_sel: list of GPIOs which can act as chip-selects for the SPI.
* SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
* to populate if all chip-selects are internal.
* @cshold_bug: set this to true if the SPI controller on your chip requires
* a write to CSHOLD bit in between transfers (like in DM355).
* @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
* device on the bus.
*/
struct davinci_spi_platform_data {
u8 version;
u8 num_chipselect;
u8 intr_line;
u8 *chip_sel;
bool cshold_bug;
enum dma_event_q dma_event_q;
};
/**
* davinci_spi_config - Per-chip-select configuration for SPI slave devices
*
* @wdelay: amount of delay between transmissions. Measured in number of
* SPI module clocks.
* @odd_parity: polarity of parity flag at the end of transmit data stream.
* 0 - odd parity, 1 - even parity.
* @parity_enable: enable transmission of parity at end of each transmit
* data stream.
* @io_type: type of IO transfer. Choose between polled, interrupt and DMA.
* @timer_disable: disable chip-select timers (setup and hold)
* @c2tdelay: chip-select setup time. Measured in number of SPI module clocks.
* @t2cdelay: chip-select hold time. Measured in number of SPI module clocks.
* @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured
* in number of SPI clocks.
* @c2edelay: chip-select active to SPI ENAn signal active time. Measured in
* number of SPI clocks.
*/
struct davinci_spi_config {
u8 wdelay;
u8 odd_parity;
u8 parity_enable;
#define SPI_IO_TYPE_INTR 0
#define SPI_IO_TYPE_POLL 1
#define SPI_IO_TYPE_DMA 2
u8 io_type;
u8 timer_disable;
u8 c2tdelay;
u8 t2cdelay;
u8 t2edelay;
u8 c2edelay;
};
#endif /* __ARCH_ARM_DAVINCI_SPI_H */

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#ifndef __ASM_MACH_EP93XX_SPI_H
#define __ASM_MACH_EP93XX_SPI_H
struct spi_device;
/**
* struct ep93xx_spi_info - EP93xx specific SPI descriptor
* @num_chipselect: number of chip selects on this board, must be
* at least one
* @use_dma: use DMA for the transfers
*/
struct ep93xx_spi_info {
int num_chipselect;
bool use_dma;
};
/**
* struct ep93xx_spi_chip_ops - operation callbacks for SPI slave device
* @setup: setup the chip select mechanism
* @cleanup: cleanup the chip select mechanism
* @cs_control: control the device chip select
*/
struct ep93xx_spi_chip_ops {
int (*setup)(struct spi_device *spi);
void (*cleanup)(struct spi_device *spi);
void (*cs_control)(struct spi_device *spi, int value);
};
#endif /* __ASM_MACH_EP93XX_SPI_H */

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#ifndef __MACH_SPI_H_
#define __MACH_SPI_H_
/*
* struct spi_imx_master - device.platform_data for SPI controller devices.
* @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio
* pins, numbers < 0 mean internal CSPI chipselects according
* to MXC_SPI_CS(). Normally you want to use gpio based chip
* selects as the CSPI module tries to be intelligent about
* when to assert the chipselect: The CSPI module deasserts the
* chipselect once it runs out of input data. The other problem
* is that it is not possible to mix between high active and low
* active chipselects on one single bus using the internal
* chipselects. Unfortunately Freescale decided to put some
* chipselects on dedicated pins which are not usable as gpios,
* so we have to support the internal chipselects.
* @num_chipselect: ARRAY_SIZE(chipselect)
*/
struct spi_imx_master {
int *chipselect;
int num_chipselect;
};
#define MXC_SPI_CS(no) ((no) - 32)
#endif /* __MACH_SPI_H_*/

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@@ -0,0 +1,35 @@
/*
* arch/arm/mach-w90x900/include/mach/nuc900_spi.h
*
* Copyright (c) 2009 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_SPI_H
#define __ASM_ARCH_SPI_H
extern void mfp_set_groupg(struct device *dev, const char *subname);
struct nuc900_spi_info {
unsigned int num_cs;
unsigned int lsb;
unsigned int txneg;
unsigned int rxneg;
unsigned int divider;
unsigned int sleep;
unsigned int txnum;
unsigned int txbitlen;
int bus_num;
};
struct nuc900_spi_chip {
unsigned char bits_per_word;
};
#endif /* __ASM_ARCH_SPI_H */

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/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
*
* Copyright (C) 2009 Samsung Electronics Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __S3C64XX_PLAT_SPI_H
#define __S3C64XX_PLAT_SPI_H
struct platform_device;
/**
* struct s3c64xx_spi_csinfo - ChipSelect description
* @fb_delay: Slave specific feedback delay.
* Refer to FB_CLK_SEL register definition in SPI chapter.
* @line: Custom 'identity' of the CS line.
*
* This is per SPI-Slave Chipselect information.
* Allocate and initialize one in machine init code and make the
* spi_board_info.controller_data point to it.
*/
struct s3c64xx_spi_csinfo {
u8 fb_delay;
unsigned line;
};
/**
* struct s3c64xx_spi_info - SPI Controller defining structure
* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
* @num_cs: Number of CS this controller emulates.
* @cfg_gpio: Configure pins for this SPI controller.
*/
struct s3c64xx_spi_info {
int src_clk_nr;
int num_cs;
int (*cfg_gpio)(void);
};
/**
* s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
* initialization code.
* @cfg_gpio: Pointer to gpio setup function.
* @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
* @num_cs: Number of elements in the 'cs' array.
*
* Call this from machine init code for each SPI Controller that
* has some chips attached to it.
*/
extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
int num_cs);
extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
int num_cs);
extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
int num_cs);
/* defined by architecture to configure gpio */
extern int s3c64xx_spi0_cfg_gpio(void);
extern int s3c64xx_spi1_cfg_gpio(void);
extern int s3c64xx_spi2_cfg_gpio(void);
extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
#endif /* __S3C64XX_PLAT_SPI_H */

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/* arch/arm/plat-samsung/include/plat/ts.h
*
* Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_TS_H
#define __ASM_ARM_TS_H
struct s3c2410_ts_mach_info {
int delay;
int presc;
int oversampling_shift;
void (*cfg_gpio)(struct platform_device *dev);
};
extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *);
/* defined by architecture to configure gpio */
extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev);
#endif /* __ASM_ARM_TS_H */

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/*
* USB related definitions
*
* Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __ASM_ARCH_USB_H
#define __ASM_ARCH_USB_H
/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
#define CFGCHIP2_PHYCLKGD (1 << 17)
#define CFGCHIP2_VBUSSENSE (1 << 16)
#define CFGCHIP2_RESET (1 << 15)
#define CFGCHIP2_OTGMODE (3 << 13)
#define CFGCHIP2_NO_OVERRIDE (0 << 13)
#define CFGCHIP2_FORCE_HOST (1 << 13)
#define CFGCHIP2_FORCE_DEVICE (2 << 13)
#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
#define CFGCHIP2_PHYPWRDN (1 << 10)
#define CFGCHIP2_OTGPWRDN (1 << 9)
#define CFGCHIP2_DATPOL (1 << 8)
#define CFGCHIP2_USB1SUSPENDM (1 << 7)
#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
#define CFGCHIP2_REFFREQ (0xf << 0)
#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
struct da8xx_ohci_root_hub;
typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
unsigned port);
/* Passed as the platform data to the OHCI driver */
struct da8xx_ohci_root_hub {
/* Switch the port power on/off */
int (*set_power)(unsigned port, int on);
/* Read the port power status */
int (*get_power)(unsigned port);
/* Read the port over-current indicator */
int (*get_oci)(unsigned port);
/* Over-current indicator change notification (pass NULL to disable) */
int (*ocic_notify)(da8xx_ocic_handler_t handler);
/* Time from power on to power good (in 2 ms units) */
u8 potpgt;
};
void davinci_setup_usb(unsigned mA, unsigned potpgt_ms);
#endif /* ifndef __ASM_ARCH_USB_H */

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#ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H
#define __INCLUDE_ASM_ARCH_MXC_EHCI_H
/* values for portsc field */
#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
#define MXC_EHCI_FORCE_FS (1 << 24)
#define MXC_EHCI_UTMI_8BIT (0 << 28)
#define MXC_EHCI_UTMI_16BIT (1 << 28)
#define MXC_EHCI_SERIAL (1 << 29)
#define MXC_EHCI_MODE_UTMI (0 << 30)
#define MXC_EHCI_MODE_PHILIPS (1 << 30)
#define MXC_EHCI_MODE_ULPI (2 << 30)
#define MXC_EHCI_MODE_SERIAL (3 << 30)
/* values for flags field */
#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
#define MXC_EHCI_INTERFACE_MASK (0xf)
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
#define MXC_EHCI_TTL_ENABLED (1 << 8)
#define MXC_EHCI_INTERNAL_PHY (1 << 9)
#define MXC_EHCI_IPPUE_DOWN (1 << 10)
#define MXC_EHCI_IPPUE_UP (1 << 11)
#define MXC_EHCI_WAKEUP_ENABLED (1 << 12)
#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13)
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
#define MXC_USBH2CTRL_OFFSET 0x14
#define MX5_USBOTHER_REGS_OFFSET 0x800
/* USB_PHY_CTRL_FUNC2*/
#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3
#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0
struct mxc_usbh_platform_data {
int (*init)(struct platform_device *pdev);
int (*exit)(struct platform_device *pdev);
unsigned int portsc;
struct usb_phy *otg;
};
int mx51_initialize_usb_hw(int port, unsigned int flags);
int mx25_initialize_usb_hw(int port, unsigned int flags);
int mx31_initialize_usb_hw(int port, unsigned int flags);
int mx35_initialize_usb_hw(int port, unsigned int flags);
int mx27_initialize_usb_hw(int port, unsigned int flags);
#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */

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/*
* arch/arm/plat-orion/include/plat/ehci-orion.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_EHCI_ORION_H
#define __PLAT_EHCI_ORION_H
#include <linux/mbus.h>
enum orion_ehci_phy_ver {
EHCI_PHY_ORION,
EHCI_PHY_DD,
EHCI_PHY_KW,
EHCI_PHY_NA,
};
struct orion_ehci_data {
enum orion_ehci_phy_ver phy_version;
};
#endif

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/*
* Copyright (C) 2011 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PLAT_SAMSUNG_EHCI_H
#define __PLAT_SAMSUNG_EHCI_H __FILE__
struct s5p_ehci_platdata {
int (*phy_init)(struct platform_device *pdev, int type);
int (*phy_exit)(struct platform_device *pdev, int type);
};
extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
#endif /* __PLAT_SAMSUNG_EHCI_H */

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@@ -0,0 +1,21 @@
/*
* Copyright (C) 2011 Samsung Electronics Co.Ltd
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __MACH_EXYNOS_OHCI_H
#define __MACH_EXYNOS_OHCI_H
struct exynos4_ohci_platdata {
int (*phy_init)(struct platform_device *pdev, int type);
int (*phy_exit)(struct platform_device *pdev, int type);
};
extern void exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd);
#endif /* __MACH_EXYNOS_OHCI_H */

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@@ -0,0 +1,23 @@
/*
* Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MXC_USB
#define __ASM_ARCH_MXC_USB
struct imxusb_platform_data {
int (*init)(struct device *);
void (*exit)(struct device *);
};
#endif /* __ASM_ARCH_MXC_USB */

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@@ -0,0 +1,25 @@
/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __ASM_ARCH_USB_H
#define __ASM_ARCH_USB_H
#include <linux/dmaengine.h>
#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
struct ux500_musb_board_data {
void **dma_rx_param_array;
void **dma_tx_param_array;
u32 num_rx_channels;
u32 num_tx_channels;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
};
void ux500_add_usb(struct device *parent, resource_size_t base,
int irq, int *dma_rx_cfg, int *dma_tx_cfg);
#endif

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@@ -0,0 +1,38 @@
/*
* Copyright (C) 2009 Martin Fuzzey <mfuzzey@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MX21_USBH
#define __ASM_ARCH_MX21_USBH
enum mx21_usbh_xcvr {
/* Values below as used by hardware (HWMODE register) */
MX21_USBXCVR_TXDIF_RXDIF = 0,
MX21_USBXCVR_TXDIF_RXSE = 1,
MX21_USBXCVR_TXSE_RXDIF = 2,
MX21_USBXCVR_TXSE_RXSE = 3,
};
struct mx21_usbh_platform_data {
enum mx21_usbh_xcvr host_xcvr; /* tranceiver mode host 1,2 ports */
enum mx21_usbh_xcvr otg_xcvr; /* tranceiver mode otg (as host) port */
u16 enable_host1:1,
enable_host2:1,
enable_otg_host:1, /* enable "OTG" port (as host) */
host1_xcverless:1, /* traceiverless host1 port */
host1_txenoe:1, /* output enable host1 transmit enable */
otg_ext_xcvr:1, /* external tranceiver for OTG port */
unused:10;
};
#endif /* __ASM_ARCH_MX21_USBH */

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#ifndef ASMARM_ARCH_OHCI_H
#define ASMARM_ARCH_OHCI_H
struct device;
struct pxaohci_platform_data {
int (*init)(struct device *);
void (*exit)(struct device *);
unsigned long flags;
#define ENABLE_PORT1 (1 << 0)
#define ENABLE_PORT2 (1 << 1)
#define ENABLE_PORT3 (1 << 2)
#define ENABLE_PORT_ALL (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3)
#define POWER_SENSE_LOW (1 << 3)
#define POWER_CONTROL_LOW (1 << 4)
#define NO_OC_PROTECTION (1 << 5)
#define OC_MODE_GLOBAL (0 << 6)
#define OC_MODE_PERPORT (1 << 6)
int power_on_delay; /* Power On to Power Good time - in ms
* HCD must wait for this duration before
* accessing a powered on port
*/
int port_mode;
#define PMM_NPS_MODE 1
#define PMM_GLOBAL_MODE 2
#define PMM_PERPORT_MODE 3
int power_budget;
};
extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
#endif

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/* arch/arm/plat-samsung/include/plat/usb-control.h
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - USB host port information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_USBCONTROL_H
#define __ASM_ARCH_USBCONTROL_H
#define S3C_HCDFLG_USED (1)
struct s3c2410_hcd_port {
unsigned char flags;
unsigned char power;
unsigned char oc_status;
unsigned char oc_changed;
};
struct s3c2410_hcd_info {
struct usb_hcd *hcd;
struct s3c2410_hcd_port port[2];
void (*power_control)(int port, int to);
void (*enable_oc)(struct s3c2410_hcd_info *, int on);
void (*report_oc)(struct s3c2410_hcd_info *, int ports);
};
static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
{
if (info->report_oc != NULL) {
(info->report_oc)(info, ports);
}
}
extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info);
#endif /*__ASM_ARCH_USBCONTROL_H */

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/*
* PXA3xx U2D header
*
* Copyright (C) 2010 CompuLab Ltd.
*
* Igor Grinberg <grinberg@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PXA310_U2D__
#define __PXA310_U2D__
#include <linux/usb/ulpi.h>
struct pxa3xx_u2d_platform_data {
#define ULPI_SER_6PIN (1 << 0)
#define ULPI_SER_3PIN (1 << 1)
unsigned int ulpi_mode;
int (*init)(struct device *);
void (*exit)(struct device *);
};
/* Start PXA3xx U2D host */
int pxa3xx_u2d_start_hc(struct usb_bus *host);
/* Stop PXA3xx U2D host */
void pxa3xx_u2d_stop_hc(struct usb_bus *host);
extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
#endif /* __PXA310_U2D__ */

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/* arch/arm/plat-samsung/include/plat/udc.h
*
* Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
* Changelog:
* 14-Mar-2005 RTP Created file
* 02-Aug-2005 RTP File rename
* 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
* 18-Jan-2007 HMW Add per-platform vbus_draw function
*/
#ifndef __ASM_ARM_ARCH_UDC_H
#define __ASM_ARM_ARCH_UDC_H
enum s3c2410_udc_cmd_e {
S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
};
struct s3c2410_udc_mach_info {
void (*udc_command)(enum s3c2410_udc_cmd_e);
void (*vbus_draw)(unsigned int ma);
unsigned int pullup_pin;
unsigned int pullup_pin_inverted;
unsigned int vbus_pin;
unsigned char vbus_pin_inverted;
};
extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
struct s3c24xx_hsudc_platdata;
extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
#endif /* __ASM_ARM_ARCH_UDC_H */

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/*
* arch/arm/mach-ep93xx/include/mach/fb.h
*/
#ifndef __ASM_ARCH_EP93XXFB_H
#define __ASM_ARCH_EP93XXFB_H
struct platform_device;
struct fb_videomode;
struct fb_info;
#define EP93XXFB_USE_MODEDB 0
/* VideoAttributes flags */
#define EP93XXFB_STATE_MACHINE_ENABLE (1 << 0)
#define EP93XXFB_PIXEL_CLOCK_ENABLE (1 << 1)
#define EP93XXFB_VSYNC_ENABLE (1 << 2)
#define EP93XXFB_PIXEL_DATA_ENABLE (1 << 3)
#define EP93XXFB_COMPOSITE_SYNC (1 << 4)
#define EP93XXFB_SYNC_VERT_HIGH (1 << 5)
#define EP93XXFB_SYNC_HORIZ_HIGH (1 << 6)
#define EP93XXFB_SYNC_BLANK_HIGH (1 << 7)
#define EP93XXFB_PCLK_FALLING (1 << 8)
#define EP93XXFB_ENABLE_AC (1 << 9)
#define EP93XXFB_ENABLE_LCD (1 << 10)
#define EP93XXFB_ENABLE_CCIR (1 << 12)
#define EP93XXFB_USE_PARALLEL_INTERFACE (1 << 13)
#define EP93XXFB_ENABLE_INTERRUPT (1 << 14)
#define EP93XXFB_USB_INTERLACE (1 << 16)
#define EP93XXFB_USE_EQUALIZATION (1 << 17)
#define EP93XXFB_USE_DOUBLE_HORZ (1 << 18)
#define EP93XXFB_USE_DOUBLE_VERT (1 << 19)
#define EP93XXFB_USE_BLANK_PIXEL (1 << 20)
#define EP93XXFB_USE_SDCSN0 (0 << 21)
#define EP93XXFB_USE_SDCSN1 (1 << 21)
#define EP93XXFB_USE_SDCSN2 (2 << 21)
#define EP93XXFB_USE_SDCSN3 (3 << 21)
#define EP93XXFB_ENABLE (EP93XXFB_STATE_MACHINE_ENABLE | \
EP93XXFB_PIXEL_CLOCK_ENABLE | \
EP93XXFB_VSYNC_ENABLE | \
EP93XXFB_PIXEL_DATA_ENABLE)
struct ep93xxfb_mach_info {
unsigned int num_modes;
const struct fb_videomode *modes;
const struct fb_videomode *default_mode;
int bpp;
unsigned int flags;
int (*setup)(struct platform_device *pdev);
void (*teardown)(struct platform_device *pdev);
void (*blank)(int blank_mode, struct fb_info *info);
};
#endif /* __ASM_ARCH_EP93XXFB_H */

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/*
* This structure describes the machine which we are running on.
*/
#ifndef __MACH_IMXFB_H__
#define __MACH_IMXFB_H__
#include <linux/fb.h>
#define PCR_TFT (1 << 31)
#define PCR_COLOR (1 << 30)
#define PCR_PBSIZ_1 (0 << 28)
#define PCR_PBSIZ_2 (1 << 28)
#define PCR_PBSIZ_4 (2 << 28)
#define PCR_PBSIZ_8 (3 << 28)
#define PCR_BPIX_1 (0 << 25)
#define PCR_BPIX_2 (1 << 25)
#define PCR_BPIX_4 (2 << 25)
#define PCR_BPIX_8 (3 << 25)
#define PCR_BPIX_12 (4 << 25)
#define PCR_BPIX_16 (5 << 25)
#define PCR_BPIX_18 (6 << 25)
#define PCR_PIXPOL (1 << 24)
#define PCR_FLMPOL (1 << 23)
#define PCR_LPPOL (1 << 22)
#define PCR_CLKPOL (1 << 21)
#define PCR_OEPOL (1 << 20)
#define PCR_SCLKIDLE (1 << 19)
#define PCR_END_SEL (1 << 18)
#define PCR_END_BYTE_SWAP (1 << 17)
#define PCR_REV_VS (1 << 16)
#define PCR_ACD_SEL (1 << 15)
#define PCR_ACD(x) (((x) & 0x7f) << 8)
#define PCR_SCLK_SEL (1 << 7)
#define PCR_SHARP (1 << 6)
#define PCR_PCD(x) ((x) & 0x3f)
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
#define PWMR_LDMSK (1 << 15)
#define PWMR_SCR1 (1 << 10)
#define PWMR_SCR0 (1 << 9)
#define PWMR_CC_EN (1 << 8)
#define PWMR_PW(x) ((x) & 0xff)
#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
#define LSCR1_GRAY1(x) (((x) & 0xf))
#define DMACR_BURST (1 << 31)
#define DMACR_HM(x) (((x) & 0xf) << 16)
#define DMACR_TM(x) ((x) & 0xf)
struct imx_fb_videomode {
struct fb_videomode mode;
u32 pcr;
unsigned char bpp;
};
struct imx_fb_platform_data {
struct imx_fb_videomode *mode;
int num_modes;
u_int cmap_greyscale:1,
cmap_inverse:1,
cmap_static:1,
unused:29;
u_int pwmr;
u_int lscr1;
u_int dmacr;
u_char * fixed_screen_cpu;
dma_addr_t fixed_screen_dma;
int (*init)(struct platform_device *);
void (*exit)(struct platform_device *);
void (*lcd_power)(int);
void (*backlight_power)(int);
};
void set_imx_fb_info(struct imx_fb_platform_data *);
#endif /* ifndef __MACH_IMXFB_H__ */

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/* arch/arm/mach-msm/include/mach/msm_fb.h
*
* Internal shared definitions for various MSM framebuffer parts.
*
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MSM_FB_H_
#define _MSM_FB_H_
#include <linux/device.h>
struct mddi_info;
struct msm_fb_data {
int xres; /* x resolution in pixels */
int yres; /* y resolution in pixels */
int width; /* disply width in mm */
int height; /* display height in mm */
unsigned output_format;
};
struct msmfb_callback {
void (*func)(struct msmfb_callback *);
};
enum {
MSM_MDDI_PMDH_INTERFACE,
MSM_MDDI_EMDH_INTERFACE,
MSM_EBI2_INTERFACE,
};
#define MSMFB_CAP_PARTIAL_UPDATES (1 << 0)
struct msm_panel_data {
/* turns off the fb memory */
int (*suspend)(struct msm_panel_data *);
/* turns on the fb memory */
int (*resume)(struct msm_panel_data *);
/* turns off the panel */
int (*blank)(struct msm_panel_data *);
/* turns on the panel */
int (*unblank)(struct msm_panel_data *);
void (*wait_vsync)(struct msm_panel_data *);
void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *);
void (*clear_vsync)(struct msm_panel_data *);
/* from the enum above */
unsigned interface_type;
/* data to be passed to the fb driver */
struct msm_fb_data *fb_data;
/* capabilities supported by the panel */
uint32_t caps;
};
struct msm_mddi_client_data {
void (*suspend)(struct msm_mddi_client_data *);
void (*resume)(struct msm_mddi_client_data *);
void (*activate_link)(struct msm_mddi_client_data *);
void (*remote_write)(struct msm_mddi_client_data *, uint32_t val,
uint32_t reg);
uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg);
void (*auto_hibernate)(struct msm_mddi_client_data *, int);
/* custom data that needs to be passed from the board file to a
* particular client */
void *private_client_data;
struct resource *fb_resource;
/* from the list above */
unsigned interface_type;
};
struct msm_mddi_platform_data {
unsigned int clk_rate;
void (*power_client)(struct msm_mddi_client_data *, int on);
/* fixup the mfr name, product id */
void (*fixup)(uint16_t *mfr_name, uint16_t *product_id);
struct resource *fb_resource; /*optional*/
/* number of clients in the list that follows */
int num_clients;
/* array of client information of clients */
struct {
unsigned product_id; /* mfr id in top 16 bits, product id
* in lower 16 bits
*/
char *name; /* the device name will be the platform
* device name registered for the client,
* it should match the name of the associated
* driver
*/
unsigned id; /* id for mddi client device node, will also
* be used as device id of panel devices, if
* the client device will have multiple panels
* space must be left here for them
*/
void *client_data; /* required private client data */
unsigned int clk_rate; /* optional: if the client requires a
* different mddi clk rate
*/
} client_platform_data[];
};
struct mdp_blit_req;
struct fb_info;
struct mdp_device {
struct device dev;
void (*dma)(struct mdp_device *mpd, uint32_t addr,
uint32_t stride, uint32_t w, uint32_t h, uint32_t x,
uint32_t y, struct msmfb_callback *callback, int interface);
void (*dma_wait)(struct mdp_device *mdp);
int (*blit)(struct mdp_device *mdp, struct fb_info *fb,
struct mdp_blit_req *req);
void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id);
};
struct class_interface;
int register_mdp_client(struct class_interface *class_intf);
/**** private client data structs go below this line ***/
struct msm_mddi_bridge_platform_data {
/* from board file */
int (*init)(struct msm_mddi_bridge_platform_data *,
struct msm_mddi_client_data *);
int (*uninit)(struct msm_mddi_bridge_platform_data *,
struct msm_mddi_client_data *);
/* passed to panel for use by the fb driver */
int (*blank)(struct msm_mddi_bridge_platform_data *,
struct msm_mddi_client_data *);
int (*unblank)(struct msm_mddi_bridge_platform_data *,
struct msm_mddi_client_data *);
struct msm_fb_data fb_data;
};
#endif

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/*
* Copyright (C) 2008
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MX3FB_H__
#define __ASM_ARCH_MX3FB_H__
#include <linux/device.h>
#include <linux/fb.h>
/* Proprietary FB_SYNC_ flags */
#define FB_SYNC_OE_ACT_HIGH 0x80000000
#define FB_SYNC_CLK_INVERT 0x40000000
#define FB_SYNC_DATA_INVERT 0x20000000
#define FB_SYNC_CLK_IDLE_EN 0x10000000
#define FB_SYNC_SHARP_MODE 0x08000000
#define FB_SYNC_SWAP_RGB 0x04000000
#define FB_SYNC_CLK_SEL_EN 0x02000000
/*
* Specify the way your display is connected. The IPU can arbitrarily
* map the internal colors to the external data lines. We only support
* the following mappings at the moment.
*/
enum disp_data_mapping {
/* blue -> d[0..5], green -> d[6..11], red -> d[12..17] */
IPU_DISP_DATA_MAPPING_RGB666,
/* blue -> d[0..4], green -> d[5..10], red -> d[11..15] */
IPU_DISP_DATA_MAPPING_RGB565,
/* blue -> d[0..7], green -> d[8..15], red -> d[16..23] */
IPU_DISP_DATA_MAPPING_RGB888,
};
/**
* struct mx3fb_platform_data - mx3fb platform data
*
* @dma_dev: pointer to the dma-device, used for dma-slave connection
* @mode: pointer to a platform-provided per mxc_register_fb() videomode
*/
struct mx3fb_platform_data {
struct device *dma_dev;
const char *name;
const struct fb_videomode *mode;
int num_modes;
enum disp_data_mapping disp_data_fmt;
};
#endif

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/* linux/include/asm/arch-nuc900/fb.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Changelog:
*
* 2008/08/26 vincen.zswan modify this file for LCD.
*/
#ifndef __ASM_ARM_FB_H
#define __ASM_ARM_FB_H
/* LCD Controller Hardware Desc */
struct nuc900fb_hw {
unsigned int lcd_dccs;
unsigned int lcd_device_ctrl;
unsigned int lcd_mpulcd_cmd;
unsigned int lcd_int_cs;
unsigned int lcd_crtc_size;
unsigned int lcd_crtc_dend;
unsigned int lcd_crtc_hr;
unsigned int lcd_crtc_hsync;
unsigned int lcd_crtc_vr;
unsigned int lcd_va_baddr0;
unsigned int lcd_va_baddr1;
unsigned int lcd_va_fbctrl;
unsigned int lcd_va_scale;
unsigned int lcd_va_test;
unsigned int lcd_va_win;
unsigned int lcd_va_stuff;
};
/* LCD Display Description */
struct nuc900fb_display {
/* LCD Image type */
unsigned type;
/* LCD Screen Size */
unsigned short width;
unsigned short height;
/* LCD Screen Info */
unsigned short xres;
unsigned short yres;
unsigned short bpp;
unsigned long pixclock;
unsigned short left_margin;
unsigned short right_margin;
unsigned short hsync_len;
unsigned short upper_margin;
unsigned short lower_margin;
unsigned short vsync_len;
/* hardware special register value */
unsigned int dccs;
unsigned int devctl;
unsigned int fbctrl;
unsigned int scale;
};
struct nuc900fb_mach_info {
struct nuc900fb_display *displays;
unsigned num_displays;
unsigned default_display;
/* GPIO Setting Info */
unsigned gpio_dir;
unsigned gpio_dir_mask;
unsigned gpio_data;
unsigned gpio_data_mask;
};
extern void __init nuc900_fb_set_platdata(struct nuc900fb_mach_info *);
#endif /* __ASM_ARM_FB_H */

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/*
* arch/arm/mach-pxa/include/mach/pxafb.h
*
* Support for the xscale frame buffer.
*
* Author: Jean-Frederic Clere
* Created: Sep 22, 2003
* Copyright: jfclere@sinix.net
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
#include <mach/regs-lcd.h>
/*
* Supported LCD connections
*
* bits 0 - 3: for LCD panel type:
*
* STN - for passive matrix
* DSTN - for dual scan passive matrix
* TFT - for active matrix
*
* bits 4 - 9 : for bus width
* bits 10-17 : for AC Bias Pin Frequency
* bit 18 : for output enable polarity
* bit 19 : for pixel clock edge
* bit 20 : for output pixel format when base is RGBT16
*/
#define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
#define LCD_TYPE_MASK 0xf
#define LCD_TYPE_UNKNOWN 0
#define LCD_TYPE_MONO_STN 1
#define LCD_TYPE_MONO_DSTN 2
#define LCD_TYPE_COLOR_STN 3
#define LCD_TYPE_COLOR_DSTN 4
#define LCD_TYPE_COLOR_TFT 5
#define LCD_TYPE_SMART_PANEL 6
#define LCD_TYPE_MAX 7
#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
#define LCD_BIAS_ACTIVE_HIGH (0 << 18)
#define LCD_BIAS_ACTIVE_LOW (1 << 18)
#define LCD_PCLK_EDGE_RISE (0 << 19)
#define LCD_PCLK_EDGE_FALL (1 << 19)
#define LCD_ALTERNATE_MAPPING (1 << 20)
/*
* This structure describes the machine which we are running on.
* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
* of linux/drivers/video/pxafb.c
*/
struct pxafb_mode_info {
u_long pixclock;
u_short xres;
u_short yres;
u_char bpp;
u_int cmap_greyscale:1,
depth:8,
transparency:1,
unused:22;
/* Parallel Mode Timing */
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len;
u_char upper_margin;
u_char lower_margin;
u_char sync;
/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
* Note:
* 1. all parameters in nanosecond (ns)
* 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
* in pxa27x and pxa3xx, initialize them to the same value or
* the larger one will be used
* 3. same to {rd,wr}_pulse_width
*
* 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
* 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
* 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
*/
unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
unsigned cmd_inh_time; /* Command Inhibit time between two writes */
unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
};
struct pxafb_mach_info {
struct pxafb_mode_info *modes;
unsigned int num_modes;
unsigned int lcd_conn;
unsigned long video_mem_size;
u_int fixed_modes:1,
cmap_inverse:1,
cmap_static:1,
acceleration_enabled:1,
unused:28;
/* The following should be defined in LCCR0
* LCCR0_Act or LCCR0_Pas Active or Passive
* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
* LCCR0_Mono or LCCR0_Color Mono/Color
* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
* LCCR0_DMADel(Tcpu) (optional) DMA request delay
*
* The following should not be defined in LCCR0:
* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
*/
u_int lccr0;
/* The following should be defined in LCCR3
* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
* LCCR3_Acb(X) AB Bias pin frequency
* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
*
* The following should not be defined in LCCR3
* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
*/
u_int lccr3;
/* The following should be defined in LCCR4
* LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
*
* All other bits in LCCR4 should be left alone.
*/
u_int lccr4;
void (*pxafb_backlight_power)(int);
void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
void (*smart_update)(struct fb_info *);
};
void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
unsigned long pxafb_get_hsync_time(struct device *dev);
#ifdef CONFIG_FB_PXA_SMARTPANEL
extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
extern int pxafb_smart_flush(struct fb_info *info);
#else
static inline int pxafb_smart_queue(struct fb_info *info,
uint16_t *cmds, int n)
{
return 0;
}
static inline int pxafb_smart_flush(struct fb_info *info)
{
return 0;
}
#endif

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/*
* VT8500/WM8505 Frame Buffer platform data definitions
*
* Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _VT8500FB_H
#define _VT8500FB_H
#include <linux/fb.h>
struct vt8500fb_platform_data {
struct fb_videomode mode;
u32 xres_virtual;
u32 yres_virtual;
u32 bpp;
unsigned long video_mem_phys;
void *video_mem_virt;
unsigned long video_mem_len;
};
#endif /* _VT8500FB_H */