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media: v4l2-dv-timings.c: fix wrong condition in two for-loops

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[ Upstream commit 4108b3e6db31acc4c68133290bbcc87d4db905c9 ]

These for-loops should test against v4l2_dv_timings_presets[i].bt.width,
not if i < v4l2_dv_timings_presets[i].bt.width. Luckily nothing ever broke,
since the smallest width is still a lot higher than the total number of
presets, but it is wrong.

The last item in the presets array is all 0, so the for-loop must stop
when it reaches that sentinel.

Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Reported-by: Krzysztof Hałasa <khalasa@piap.pl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Hans Verkuil
2021-07-23 10:22:59 +02:00
committed by Greg Kroah-Hartman
parent ac1bcf53e3
commit e3a2e20ed5
1 changed files with 2 additions and 2 deletions
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4
drivers/media/v4l2-core/v4l2-dv-timings.c
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@@ -196,7 +196,7 @@ bool v4l2_find_dv_timings_cap(struct v4l2_dv_timings *t,
if (!v4l2_valid_dv_timings(t, cap, fnc, fnc_handle)) if (!v4l2_valid_dv_timings(t, cap, fnc, fnc_handle))
return false; return false;
for (i = 0; i < v4l2_dv_timings_presets[i].bt.width; i++) { for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
if (v4l2_valid_dv_timings(v4l2_dv_timings_presets + i, cap, if (v4l2_valid_dv_timings(v4l2_dv_timings_presets + i, cap,
fnc, fnc_handle) && fnc, fnc_handle) &&
v4l2_match_dv_timings(t, v4l2_dv_timings_presets + i, v4l2_match_dv_timings(t, v4l2_dv_timings_presets + i,
@@ -218,7 +218,7 @@ bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic)
{ {
unsigned int i; unsigned int i;
for (i = 0; i < v4l2_dv_timings_presets[i].bt.width; i++) { for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
const struct v4l2_bt_timings *bt = const struct v4l2_bt_timings *bt =
&v4l2_dv_timings_presets[i].bt; &v4l2_dv_timings_presets[i].bt;