Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (41 commits) m68knommu: external interrupt support to ColdFire intc-simr controller m68knommu: external interrupt support to ColdFire intc-2 controller m68knommu: remove ColdFire CLOCK_DIV config option m68knommu: fix gpio warnings for ColdFire 5407 targets m68knommu: fix gpio warnings for ColdFire 532x targets m68knommu: fix gpio warnings for ColdFire 5307 targets m68knommu: fix gpio warnings for ColdFire 527x targets m68knommu: fix gpio warnings for ColdFire 5272 targets m68knommu: fix gpio warnings for ColdFire 5249 targets m68knommu: fix gpio warnings for ColdFire 523x targets m68knommu: fix gpio warnings for ColdFire 520x targets m68knommu: fix gpio warnings for ColdFire 5206e targets m68knommu: fix gpio warnings for ColdFire 5206 targets m68knommu: fixing compiler warnings m68knommu: limit interrupts supported by ColdFire intc-simr driver m68knommu: move some init code out of unmask routine for ColdFire intc-2 m68knommu: limit interrupts supported by ColdFire intc-2 driver m68knommu: add basic support for the ColdFire based FireBee board m68knommu: make ColdFire internal peripheral region configurable m68knommu: clean up definitions of ColdFire peripheral base registers ...
This commit is contained in:
Linus Torvalds
@@ -14,39 +14,35 @@
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/*
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* Define master clock frequency. This is essentially done at config
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* time now. No point enumerating dozens of possible clock options
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* here. Also the peripheral clock (bus clock) divide ratio is set
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* at config time too.
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* Define master clock frequency. This is done at config time now.
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* No point enumerating dozens of possible clock options here. And
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* in any case new boards come along from time to time that have yet
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* another different clocking frequency.
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*/
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#ifdef CONFIG_CLOCK_SET
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#define MCF_CLK CONFIG_CLOCK_FREQ
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#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
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#else
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#error "Don't know what your ColdFire CPU clock frequency is??"
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#endif
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/*
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* Define the processor support peripherals base address.
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* This is generally setup by the boards start up code.
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* Define the processor internal peripherals base address.
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*
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* The majority of ColdFire parts use an MBAR register to set
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* the base address. Some have an IPSBAR register instead, and it
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* has slightly different rules on its size and alignment. Some
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* parts have fixed addresses and the internal peripherals cannot
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* be relocated in the CPU address space.
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*
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* The value of MBAR or IPSBAR is config time selectable, we no
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* longer hard define it here. No MBAR or IPSBAR will be defined if
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* this part has a fixed peripheral address map.
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*/
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#define MCF_MBAR 0x10000000
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#define MCF_MBAR2 0x80000000
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#if defined(CONFIG_M54xx)
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#define MCF_IPSBAR MCF_MBAR
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#elif defined(CONFIG_M520x)
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#define MCF_IPSBAR 0xFC000000
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#else
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#define MCF_IPSBAR 0x40000000
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#ifdef CONFIG_MBAR
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#define MCF_MBAR CONFIG_MBAR
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#endif
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x)
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#undef MCF_MBAR
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#define MCF_MBAR MCF_IPSBAR
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#elif defined(CONFIG_M532x)
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#undef MCF_MBAR
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#define MCF_MBAR 0x00000000
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#ifdef CONFIG_IPSBAR
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#define MCF_IPSBAR CONFIG_IPSBAR
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#endif
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/****************************************************************************/
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@@ -14,6 +14,7 @@
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#define CPU_NAME "COLDFIRE(m5206)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK MCF_CLK
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#include <asm/m52xxacr.h>
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@@ -48,14 +49,14 @@
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#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
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#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
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#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
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#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
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#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
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#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
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#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
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#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
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#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
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#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
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#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
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#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
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#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
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#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
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#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
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@@ -89,9 +90,15 @@
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#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
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#endif
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
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#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
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#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
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#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
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#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
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#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
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#if defined(CONFIG_NETtel)
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#define MCFUART_BASE1 0x180 /* Base address of UART1 */
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#define MCFUART_BASE2 0x140 /* Base address of UART2 */
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@@ -13,13 +13,14 @@
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#define CPU_NAME "COLDFIRE(m520x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* Define the 520x SIM register set addresses.
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*/
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#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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@@ -35,9 +36,9 @@
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* address to the SIMR and CIMR registers (not offsets into IPSBAR).
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* The 520x family only has a single INTC unit.
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*/
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#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
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#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
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#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
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#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
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#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
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#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
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#define MCFINTC1_SIMR (0)
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#define MCFINTC1_CIMR (0)
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#define MCFINTC1_ICR0 (0)
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@@ -52,19 +53,22 @@
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
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#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
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#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
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#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
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#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
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#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
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#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
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#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
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#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
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#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
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#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
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#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
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/*
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* EPORT and GPIO registers.
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*/
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#define MCFEPORT_EPPAR 0xFC088000
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#define MCFEPORT_EPDDR 0xFC088002
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#define MCFEPORT_EPIER 0xFC088003
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#define MCFEPORT_EPDR 0xFC088004
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#define MCFEPORT_EPPDR 0xFC088005
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#define MCFEPORT_EPFR 0xFC088006
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#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
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#define MCFGPIO_PODR_BE 0xFC0A4001
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@@ -119,10 +123,10 @@
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCF_GPIO_PAR_UART (0xA4036)
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#define MCF_GPIO_PAR_FECI2C (0xA4033)
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#define MCF_GPIO_PAR_QSPI (0xA4034)
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#define MCF_GPIO_PAR_FEC (0xA4038)
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#define MCF_GPIO_PAR_UART 0xFC0A4036
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#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
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#define MCF_GPIO_PAR_QSPI 0xFC0A4034
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#define MCF_GPIO_PAR_FEC 0xFC0A4038
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#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
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#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
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@@ -133,12 +137,24 @@
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#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
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#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
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/*
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* PIT timer module.
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*/
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#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
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#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
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/*
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* UART module.
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*/
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#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
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#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
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#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
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#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
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#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
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#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
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/*
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* FEC module.
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*/
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#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
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#define MCFFEC_SIZE 0x800 /* Register set size */
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/*
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* Reset Controll Unit.
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@@ -13,14 +13,16 @@
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#define CPU_NAME "COLDFIRE(m523x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* Define the 523x SIM register set addresses.
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*/
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#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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@@ -39,11 +41,11 @@
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_DCR 0x44 /* SDRAM control */
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#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
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#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
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#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
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#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
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#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
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#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
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#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
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#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
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#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
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/*
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* Reset Controll Unit (relative to IPSBAR).
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@@ -57,10 +59,19 @@
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/*
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* UART module.
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*/
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#define MCFUART_BASE1 0x200 /* Base address of UART1 */
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#define MCFUART_BASE2 0x240 /* Base address of UART2 */
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#define MCFUART_BASE3 0x280 /* Base address of UART3 */
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#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
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#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
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#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
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/*
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* FEC ethernet module.
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*/
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#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
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#define MCFFEC_SIZE 0x800
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/*
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* GPIO module.
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*/
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#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
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#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
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#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
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@@ -117,13 +128,23 @@
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#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
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#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
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/*
|
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* PIT timer base addresses.
|
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*/
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#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
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#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
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#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
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#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
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/*
|
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* EPort
|
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*/
|
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|
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#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
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#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
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#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
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#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
|
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#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
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|
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/*
|
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* Generic GPIO support
|
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@@ -143,5 +164,14 @@
|
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*/
|
||||
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
|
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#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
|
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|
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/*
|
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* DMA unit base addresses.
|
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*/
|
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#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
|
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#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
|
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#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
|
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#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
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|
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/****************************************************************************/
|
||||
#endif /* m523xsim_h */
|
||||
|
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@@ -13,9 +13,15 @@
|
||||
|
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#define CPU_NAME "COLDFIRE(m5249)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
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#include <asm/m52xxacr.h>
|
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|
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/*
|
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* The 5249 has a second MBAR region, define its address.
|
||||
*/
|
||||
#define MCF_MBAR2 0x80000000
|
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|
||||
/*
|
||||
* Define the 5249 SIM register set addresses.
|
||||
*/
|
||||
@@ -55,11 +61,17 @@
|
||||
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
|
||||
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
|
||||
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
|
||||
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
|
||||
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
|
||||
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
|
||||
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
|
||||
|
||||
/*
|
||||
* Timer module.
|
||||
*/
|
||||
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
|
||||
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
|
||||
|
||||
/*
|
||||
* UART module.
|
||||
@@ -67,6 +79,14 @@
|
||||
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
|
||||
|
||||
/*
|
||||
* DMA unit base addresses.
|
||||
*/
|
||||
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
|
||||
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
|
||||
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
|
||||
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
|
||||
|
||||
/*
|
||||
* Some symbol defines for the above...
|
||||
*/
|
||||
|
||||
@@ -14,6 +14,7 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m5272)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK MCF_CLK
|
||||
|
||||
#include <asm/m52xxacr.h>
|
||||
|
||||
@@ -80,6 +81,13 @@
|
||||
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
|
||||
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
|
||||
|
||||
#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
|
||||
|
||||
#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
|
||||
#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
|
||||
#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
|
||||
#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
|
||||
|
||||
/*
|
||||
* Define system peripheral IRQ usage.
|
||||
*/
|
||||
|
||||
@@ -13,14 +13,16 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m527x)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
||||
#include <asm/m52xxacr.h>
|
||||
|
||||
/*
|
||||
* Define the 5270/5271 SIM register set addresses.
|
||||
*/
|
||||
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
|
||||
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
|
||||
|
||||
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
|
||||
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
|
||||
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
|
||||
@@ -42,29 +44,45 @@
|
||||
* SDRAM configuration registers.
|
||||
*/
|
||||
#ifdef CONFIG_M5271
|
||||
#define MCFSIM_DCR 0x40 /* SDRAM control */
|
||||
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
|
||||
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
|
||||
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
|
||||
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
|
||||
#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
|
||||
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
|
||||
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
|
||||
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
|
||||
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
|
||||
#endif
|
||||
#ifdef CONFIG_M5275
|
||||
#define MCFSIM_DMR 0x40 /* SDRAM mode */
|
||||
#define MCFSIM_DCR 0x44 /* SDRAM control */
|
||||
#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
|
||||
#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
|
||||
#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
|
||||
#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
|
||||
#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
|
||||
#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
|
||||
#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
|
||||
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
|
||||
#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
|
||||
#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
|
||||
#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
|
||||
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
|
||||
#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
|
||||
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* DMA unit base addresses.
|
||||
*/
|
||||
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
|
||||
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
|
||||
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
|
||||
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
|
||||
|
||||
/*
|
||||
* UART module.
|
||||
*/
|
||||
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
|
||||
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
|
||||
#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
|
||||
#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
|
||||
#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
|
||||
|
||||
/*
|
||||
* FEC ethernet module.
|
||||
*/
|
||||
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
|
||||
#define MCFFEC_SIZE0 0x800
|
||||
#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
|
||||
#define MCFFEC_SIZE1 0x800
|
||||
|
||||
#ifdef CONFIG_M5271
|
||||
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
|
||||
@@ -230,15 +248,23 @@
|
||||
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PIT timer base addresses.
|
||||
*/
|
||||
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
|
||||
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
|
||||
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
|
||||
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
|
||||
|
||||
/*
|
||||
* EPort
|
||||
*/
|
||||
|
||||
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
|
||||
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
|
||||
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
|
||||
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
|
||||
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
|
||||
|
||||
|
||||
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
|
||||
|
||||
/*
|
||||
* GPIO pins setups to enable the UARTs.
|
||||
|
||||
@@ -13,14 +13,16 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m528x)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK MCF_CLK
|
||||
|
||||
#include <asm/m52xxacr.h>
|
||||
|
||||
/*
|
||||
* Define the 5280/5282 SIM register set addresses.
|
||||
*/
|
||||
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
|
||||
|
||||
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
|
||||
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
|
||||
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
|
||||
@@ -39,18 +41,32 @@
|
||||
/*
|
||||
* SDRAM configuration registers.
|
||||
*/
|
||||
#define MCFSIM_DCR 0x44 /* SDRAM control */
|
||||
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
|
||||
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
|
||||
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
|
||||
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
|
||||
#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
|
||||
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
|
||||
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
|
||||
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
|
||||
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
|
||||
|
||||
/*
|
||||
* DMA unit base addresses.
|
||||
*/
|
||||
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
|
||||
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
|
||||
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
|
||||
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
|
||||
|
||||
/*
|
||||
* UART module.
|
||||
*/
|
||||
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
|
||||
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
|
||||
#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
|
||||
#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
|
||||
#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
|
||||
|
||||
/*
|
||||
* FEC ethernet module.
|
||||
*/
|
||||
#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
|
||||
#define MCFFEC_SIZE 0x800
|
||||
|
||||
/*
|
||||
* GPIO registers
|
||||
@@ -162,6 +178,14 @@
|
||||
#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
|
||||
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
|
||||
|
||||
/*
|
||||
* PIT timer base addresses.
|
||||
*/
|
||||
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
|
||||
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
|
||||
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
|
||||
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
|
||||
|
||||
/*
|
||||
* Edge Port registers
|
||||
*/
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m5307)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
||||
#include <asm/m53xxacr.h>
|
||||
|
||||
@@ -89,15 +90,29 @@
|
||||
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
|
||||
#endif /* CONFIG_OLDMASK */
|
||||
|
||||
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
|
||||
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
|
||||
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
|
||||
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
|
||||
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
|
||||
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
|
||||
|
||||
/*
|
||||
* Timer module.
|
||||
*/
|
||||
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
|
||||
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
|
||||
|
||||
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
|
||||
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
|
||||
|
||||
/*
|
||||
* DMA unit base addresses.
|
||||
*/
|
||||
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
|
||||
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
|
||||
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
|
||||
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
|
||||
|
||||
/*
|
||||
* UART module.
|
||||
*/
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m532x)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK (MCF_CLK / 3)
|
||||
|
||||
#include <asm/m53xxacr.h>
|
||||
|
||||
@@ -85,6 +86,14 @@
|
||||
#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
|
||||
#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
|
||||
|
||||
/*
|
||||
* Timer module.
|
||||
*/
|
||||
#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
|
||||
#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Controller Module
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m5407)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
||||
#include <asm/m54xxacr.h>
|
||||
|
||||
@@ -72,11 +73,17 @@
|
||||
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
|
||||
|
||||
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
|
||||
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
|
||||
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
|
||||
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
|
||||
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
|
||||
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
|
||||
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
|
||||
|
||||
/*
|
||||
* Timer module.
|
||||
*/
|
||||
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
|
||||
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
|
||||
|
||||
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
|
||||
@@ -84,6 +91,14 @@
|
||||
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
|
||||
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
|
||||
|
||||
/*
|
||||
* DMA unit base addresses.
|
||||
*/
|
||||
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
|
||||
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
|
||||
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
|
||||
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
|
||||
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m54xx)"
|
||||
#define CPU_INSTR_PER_JIFFY 2
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
||||
#include <asm/m54xxacr.h>
|
||||
|
||||
@@ -15,7 +16,8 @@
|
||||
/*
|
||||
* Interrupt Controller Registers
|
||||
*/
|
||||
#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
|
||||
|
||||
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
|
||||
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
|
||||
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
|
||||
@@ -47,6 +49,16 @@
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
|
||||
/*
|
||||
* EDGE Port support.
|
||||
*/
|
||||
#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
|
||||
#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
|
||||
#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
|
||||
#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
|
||||
#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
|
||||
#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
|
||||
|
||||
/*
|
||||
* Some PSC related definitions
|
||||
*/
|
||||
|
||||
@@ -11,29 +11,6 @@
|
||||
#define mcfdma_h
|
||||
/****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Get address specific defines for this Coldfire member.
|
||||
*/
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
||||
#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
|
||||
#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
|
||||
#elif defined(CONFIG_M5272)
|
||||
#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */
|
||||
#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
|
||||
/* These are relative to the IPSBAR, not MBAR */
|
||||
#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */
|
||||
#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */
|
||||
#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */
|
||||
#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
|
||||
#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
|
||||
#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
|
||||
#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined(CONFIG_M5272)
|
||||
|
||||
/*
|
||||
|
||||
@@ -11,22 +11,8 @@
|
||||
#define mcfpit_h
|
||||
/****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Get address specific defines for the 5270/5271, 5280/5282, and 5208.
|
||||
*/
|
||||
#if defined(CONFIG_M520x)
|
||||
#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
|
||||
#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
|
||||
#else
|
||||
#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
|
||||
#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
|
||||
#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
|
||||
#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the PIT timer register set addresses.
|
||||
* Define the PIT timer register address offsets.
|
||||
*/
|
||||
#define MCFPIT_PCSR 0x0 /* PIT control register */
|
||||
#define MCFPIT_PMR 0x2 /* PIT modulus register */
|
||||
|
||||
@@ -12,29 +12,6 @@
|
||||
#define mcftimer_h
|
||||
/****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Get address specific defines for this ColdFire member.
|
||||
*/
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
||||
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
|
||||
#elif defined(CONFIG_M5272)
|
||||
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
|
||||
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
|
||||
#elif defined(CONFIG_M532x)
|
||||
#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
|
||||
#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Define the TIMER register set addresses.
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user