Merge tag 'v4.11-rc1' into omap-for-v4.11/fixes
Linux 4.11-rc1
This commit is contained in:
Tony Lindgren
@@ -78,8 +78,6 @@ int __init omap2_clk_setup_ll_ops(void)
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* OMAP2+ specific clock functions
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*/
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/* Private functions */
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/* Public functions */
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/**
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@@ -112,65 +110,6 @@ void omap2_init_clk_clkdm(struct clk_hw *hw)
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}
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}
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static int __initdata mpurate;
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/*
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* By default we use the rate set by the bootloader.
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* You can override this with mpurate= cmdline option.
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*/
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static int __init omap_clk_setup(char *str)
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{
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get_option(&str, &mpurate);
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if (!mpurate)
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return 1;
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if (mpurate < 1000)
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mpurate *= 1000000;
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return 1;
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}
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__setup("mpurate=", omap_clk_setup);
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/**
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* omap2_clk_print_new_rates - print summary of current clock tree rates
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* @hfclkin_ck_name: clk name for the off-chip HF oscillator
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* @core_ck_name: clk name for the on-chip CORE_CLK
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* @mpu_ck_name: clk name for the ARM MPU clock
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*
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* Prints a short message to the console with the HFCLKIN oscillator
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* rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
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* Called by the boot-time MPU rate switching code. XXX This is intended
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* to be handled by the OPP layer code in the near future and should be
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* removed from the clock code. No return value.
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*/
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void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name)
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{
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struct clk *hfclkin_ck, *core_ck, *mpu_ck;
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unsigned long hfclkin_rate;
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mpu_ck = clk_get(NULL, mpu_ck_name);
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if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
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return;
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core_ck = clk_get(NULL, core_ck_name);
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if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
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return;
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hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
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if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
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return;
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hfclkin_rate = clk_get_rate(hfclkin_ck);
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pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
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(hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
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(clk_get_rate(core_ck) / 1000000),
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(clk_get_rate(mpu_ck) / 1000000));
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}
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/**
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* ti_clk_init_features - init clock features struct for the SoC
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*
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@@ -64,10 +64,6 @@
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name);
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extern u16 cpu_mask;
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extern const struct clkops clkops_omap2_dflt_wait;
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@@ -315,15 +315,15 @@ void omap3_save_scratchpad_contents(void)
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scratchpad_contents.boot_config_ptr = 0x0;
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if (cpu_is_omap3630())
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scratchpad_contents.public_restore_ptr =
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virt_to_phys(omap3_restore_3630);
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__pa_symbol(omap3_restore_3630);
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else if (omap_rev() != OMAP3430_REV_ES3_0 &&
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omap_rev() != OMAP3430_REV_ES3_1 &&
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omap_rev() != OMAP3430_REV_ES3_1_2)
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scratchpad_contents.public_restore_ptr =
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virt_to_phys(omap3_restore);
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__pa_symbol(omap3_restore);
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else
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scratchpad_contents.public_restore_ptr =
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virt_to_phys(omap3_restore_es3);
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__pa_symbol(omap3_restore_es3);
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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scratchpad_contents.secure_ram_restore_ptr = 0x0;
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@@ -395,7 +395,7 @@ void omap3_save_scratchpad_contents(void)
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sdrc_block_contents.flags = 0x0;
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sdrc_block_contents.block_size = 0x0;
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arm_context_addr = virt_to_phys(omap3_arm_context);
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arm_context_addr = __pa_symbol(omap3_arm_context);
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/* Copy all the contents to the scratchpad location */
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scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
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@@ -46,8 +46,6 @@
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#define DISPC_CONTROL3 0x0848
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#define DISPC_IRQSTATUS 0x0018
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#define DSS_SYSCONFIG 0x10
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#define DSS_SYSSTATUS 0x14
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#define DSS_CONTROL 0x40
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#define DSS_SDI_CONTROL 0x44
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#define DSS_PLL_CONTROL 0x48
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@@ -76,36 +74,6 @@ static struct platform_device omap_display_device = {
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},
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};
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struct omap_dss_hwmod_data {
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const char *oh_name;
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const char *dev_name;
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const int id;
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};
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static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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};
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static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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{ "dss_dsi1", "omapdss_dsi", 0 },
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};
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static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_dsi1", "omapdss_dsi", 0 },
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{ "dss_dsi2", "omapdss_dsi", 1 },
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{ "dss_hdmi", "omapdss_hdmi", -1 },
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};
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#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
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static struct regmap *omap4_dsi_mux_syscon;
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@@ -162,104 +130,6 @@ static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
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return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
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}
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static struct platform_device *create_dss_pdev(const char *pdev_name,
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int pdev_id, const char *oh_name, void *pdata, int pdata_len,
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struct platform_device *parent)
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{
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struct platform_device *pdev;
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struct omap_device *od;
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struct omap_hwmod *ohs[1];
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struct omap_hwmod *oh;
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int r;
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up %s\n", oh_name);
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r = -ENODEV;
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goto err;
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}
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pdev = platform_device_alloc(pdev_name, pdev_id);
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if (!pdev) {
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pr_err("Could not create pdev for %s\n", pdev_name);
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r = -ENOMEM;
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goto err;
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}
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if (parent != NULL)
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pdev->dev.parent = &parent->dev;
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if (pdev->id != -1)
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dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
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else
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dev_set_name(&pdev->dev, "%s", pdev->name);
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ohs[0] = oh;
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od = omap_device_alloc(pdev, ohs, 1);
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if (IS_ERR(od)) {
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pr_err("Could not alloc omap_device for %s\n", pdev_name);
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r = -ENOMEM;
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goto err;
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}
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r = platform_device_add_data(pdev, pdata, pdata_len);
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if (r) {
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pr_err("Could not set pdata for %s\n", pdev_name);
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goto err;
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}
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r = omap_device_register(pdev);
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if (r) {
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pr_err("Could not register omap_device for %s\n", pdev_name);
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goto err;
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}
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return pdev;
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err:
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return ERR_PTR(r);
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}
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static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
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int pdev_id, void *pdata, int pdata_len,
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struct platform_device *parent)
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{
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struct platform_device *pdev;
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int r;
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pdev = platform_device_alloc(pdev_name, pdev_id);
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if (!pdev) {
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pr_err("Could not create pdev for %s\n", pdev_name);
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r = -ENOMEM;
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goto err;
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}
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if (parent != NULL)
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pdev->dev.parent = &parent->dev;
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if (pdev->id != -1)
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dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
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else
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dev_set_name(&pdev->dev, "%s", pdev->name);
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r = platform_device_add_data(pdev, pdata, pdata_len);
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if (r) {
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pr_err("Could not set pdata for %s\n", pdev_name);
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goto err;
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}
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r = platform_device_add(pdev);
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if (r) {
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pr_err("Could not register platform_device for %s\n", pdev_name);
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goto err;
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}
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return pdev;
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err:
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return ERR_PTR(r);
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}
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static enum omapdss_version __init omap_display_get_version(void)
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{
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if (cpu_is_omap24xx())
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@@ -293,132 +163,6 @@ static enum omapdss_version __init omap_display_get_version(void)
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return OMAPDSS_VER_UNKNOWN;
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}
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int __init omap_display_init(struct omap_dss_board_info *board_data)
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{
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int r = 0;
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struct platform_device *pdev;
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int i, oh_count;
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const struct omap_dss_hwmod_data *curr_dss_hwmod;
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struct platform_device *dss_pdev;
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enum omapdss_version ver;
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/* create omapdss device */
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ver = omap_display_get_version();
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if (ver == OMAPDSS_VER_UNKNOWN) {
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pr_err("DSS not supported on this SoC\n");
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return -ENODEV;
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}
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board_data->version = ver;
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board_data->dsi_enable_pads = omap_dsi_enable_pads;
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board_data->dsi_disable_pads = omap_dsi_disable_pads;
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board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
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omap_display_device.dev.platform_data = board_data;
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r = platform_device_register(&omap_display_device);
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if (r < 0) {
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pr_err("Unable to register omapdss device\n");
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return r;
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}
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/* create devices for dss hwmods */
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if (cpu_is_omap24xx()) {
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curr_dss_hwmod = omap2_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
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} else if (cpu_is_omap34xx()) {
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curr_dss_hwmod = omap3_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
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} else {
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curr_dss_hwmod = omap4_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
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}
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/*
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* First create the pdev for dss_core, which is used as a parent device
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* by the other dss pdevs. Note: dss_core has to be the first item in
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* the hwmod list.
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*/
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dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
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curr_dss_hwmod[0].id,
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curr_dss_hwmod[0].oh_name,
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board_data, sizeof(*board_data),
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NULL);
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if (IS_ERR(dss_pdev)) {
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pr_err("Could not build omap_device for %s\n",
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curr_dss_hwmod[0].oh_name);
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return PTR_ERR(dss_pdev);
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}
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||||
|
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for (i = 1; i < oh_count; i++) {
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pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
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curr_dss_hwmod[i].id,
|
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curr_dss_hwmod[i].oh_name,
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board_data, sizeof(*board_data),
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dss_pdev);
|
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|
||||
if (IS_ERR(pdev)) {
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pr_err("Could not build omap_device for %s\n",
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curr_dss_hwmod[i].oh_name);
|
||||
|
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return PTR_ERR(pdev);
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||||
}
|
||||
}
|
||||
|
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/* Create devices for DPI and SDI */
|
||||
|
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pdev = create_simple_dss_pdev("omapdss_dpi", 0,
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board_data, sizeof(*board_data), dss_pdev);
|
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if (IS_ERR(pdev)) {
|
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pr_err("Could not build platform_device for omapdss_dpi\n");
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return PTR_ERR(pdev);
|
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}
|
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|
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if (cpu_is_omap34xx()) {
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pdev = create_simple_dss_pdev("omapdss_sdi", 0,
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board_data, sizeof(*board_data), dss_pdev);
|
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if (IS_ERR(pdev)) {
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||||
pr_err("Could not build platform_device for omapdss_sdi\n");
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
}
|
||||
|
||||
/* create DRM device */
|
||||
r = omap_init_drm();
|
||||
if (r < 0) {
|
||||
pr_err("Unable to register omapdrm device\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* create vrfb device */
|
||||
r = omap_init_vrfb();
|
||||
if (r < 0) {
|
||||
pr_err("Unable to register omapvrfb device\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* create FB device */
|
||||
r = omap_init_fb();
|
||||
if (r < 0) {
|
||||
pr_err("Unable to register omapfb device\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
/* create V4L2 display device */
|
||||
r = omap_init_vout();
|
||||
if (r < 0) {
|
||||
pr_err("Unable to register omap_vout device\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dispc_disable_outputs(void)
|
||||
{
|
||||
u32 v, irq_mask = 0;
|
||||
@@ -573,7 +317,7 @@ static const char * const omapdss_compat_names[] __initconst = {
|
||||
"ti,dra7-dss",
|
||||
};
|
||||
|
||||
struct device_node * __init omapdss_find_dss_of_node(void)
|
||||
static struct device_node * __init omapdss_find_dss_of_node(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
int i;
|
||||
|
||||
@@ -31,11 +31,4 @@ int omap_init_vrfb(void);
|
||||
int omap_init_fb(void);
|
||||
int omap_init_vout(void);
|
||||
|
||||
struct device_node * __init omapdss_find_dss_of_node(void);
|
||||
|
||||
struct omap_dss_board_info;
|
||||
|
||||
/* Init with the board info */
|
||||
int omap_display_init(struct omap_dss_board_info *board_data);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -223,7 +223,15 @@ static void __init omap3_cpuinfo(void)
|
||||
* and CPU class bits.
|
||||
*/
|
||||
if (soc_is_omap3630()) {
|
||||
cpu_name = "OMAP3630";
|
||||
if (omap3_has_iva() && omap3_has_sgx()) {
|
||||
cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
|
||||
} else if (omap3_has_iva()) {
|
||||
cpu_name = "DM3725";
|
||||
} else if (omap3_has_sgx()) {
|
||||
cpu_name = "OMAP3615/AM3715";
|
||||
} else {
|
||||
cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
|
||||
}
|
||||
} else if (soc_is_am35xx()) {
|
||||
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
|
||||
} else if (soc_is_ti816x()) {
|
||||
|
||||
@@ -273,7 +273,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
|
||||
cpu_clear_prev_logic_pwrst(cpu);
|
||||
pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
|
||||
pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
|
||||
set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
|
||||
set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
|
||||
omap_pm_ops.scu_prepare(cpu, power_state);
|
||||
l2x0_pwrst_prepare(cpu, save_state);
|
||||
|
||||
@@ -325,7 +325,7 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
|
||||
|
||||
pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
|
||||
pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
|
||||
set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
|
||||
set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
|
||||
omap_pm_ops.scu_prepare(cpu, power_state);
|
||||
|
||||
/*
|
||||
@@ -467,13 +467,13 @@ void __init omap4_mpuss_early_init(void)
|
||||
sar_base = omap4_get_sar_ram_base();
|
||||
|
||||
if (cpu_is_omap443x())
|
||||
startup_pa = virt_to_phys(omap4_secondary_startup);
|
||||
startup_pa = __pa_symbol(omap4_secondary_startup);
|
||||
else if (cpu_is_omap446x())
|
||||
startup_pa = virt_to_phys(omap4460_secondary_startup);
|
||||
startup_pa = __pa_symbol(omap4460_secondary_startup);
|
||||
else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
|
||||
startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
|
||||
startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
|
||||
else
|
||||
startup_pa = virt_to_phys(omap5_secondary_startup);
|
||||
startup_pa = __pa_symbol(omap5_secondary_startup);
|
||||
|
||||
if (cpu_is_omap44xx())
|
||||
writel_relaxed(startup_pa, sar_base +
|
||||
|
||||
@@ -316,9 +316,9 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
||||
* A barrier is added to ensure that write buffer is drained
|
||||
*/
|
||||
if (omap_secure_apis_support())
|
||||
omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
|
||||
omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
|
||||
else
|
||||
writel_relaxed(virt_to_phys(cfg.startup_addr),
|
||||
writel_relaxed(__pa_symbol(cfg.startup_addr),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
}
|
||||
|
||||
|
||||
@@ -3248,6 +3248,36 @@ int __init omap_hwmod_setup_one(const char *oh_name)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_setup_earlycon_flags - set up flags for early console
|
||||
*
|
||||
* Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as
|
||||
* early concole so that hwmod core doesn't reset and keep it in idle
|
||||
* that specific uart.
|
||||
*/
|
||||
#ifdef CONFIG_SERIAL_EARLYCON
|
||||
static void __init omap_hwmod_setup_earlycon_flags(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct omap_hwmod *oh;
|
||||
const char *uart;
|
||||
|
||||
np = of_find_node_by_path("/chosen");
|
||||
if (np) {
|
||||
uart = of_get_property(np, "stdout-path", NULL);
|
||||
if (uart) {
|
||||
np = of_find_node_by_path(uart);
|
||||
if (np) {
|
||||
uart = of_get_property(np, "ti,hwmods", NULL);
|
||||
oh = omap_hwmod_lookup(uart);
|
||||
if (oh)
|
||||
oh->flags |= DEBUG_OMAPUART_FLAGS;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap_hwmod_setup_all - set up all registered IP blocks
|
||||
*
|
||||
@@ -3261,6 +3291,9 @@ static int __init omap_hwmod_setup_all(void)
|
||||
_ensure_mpu_hwmod_is_setup(NULL);
|
||||
|
||||
omap_hwmod_for_each(_init, NULL);
|
||||
#ifdef CONFIG_SERIAL_EARLYCON
|
||||
omap_hwmod_setup_earlycon_flags();
|
||||
#endif
|
||||
omap_hwmod_for_each(_setup, NULL);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1748,6 +1748,7 @@ static struct omap_hwmod omap54xx_uart1_hwmod = {
|
||||
.name = "uart1",
|
||||
.class = &omap54xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@@ -1763,6 +1764,7 @@ static struct omap_hwmod omap54xx_uart2_hwmod = {
|
||||
.name = "uart2",
|
||||
.class = &omap54xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@@ -1778,7 +1780,7 @@ static struct omap_hwmod omap54xx_uart3_hwmod = {
|
||||
.name = "uart3",
|
||||
.class = &omap54xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.flags = DEBUG_OMAP4UART3_FLAGS,
|
||||
.flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@@ -1794,7 +1796,7 @@ static struct omap_hwmod omap54xx_uart4_hwmod = {
|
||||
.name = "uart4",
|
||||
.class = &omap54xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.flags = DEBUG_OMAP4UART4_FLAGS,
|
||||
.flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@@ -1810,6 +1812,7 @@ static struct omap_hwmod omap54xx_uart5_hwmod = {
|
||||
.name = "uart5",
|
||||
.class = &omap54xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@@ -1825,6 +1828,7 @@ static struct omap_hwmod omap54xx_uart6_hwmod = {
|
||||
.name = "uart6",
|
||||
.class = &omap54xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* OMAP and TWL PMIC specific intializations.
|
||||
* OMAP and TWL PMIC specific initializations.
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated.
|
||||
* Thara Gopinath
|
||||
|
||||
@@ -484,15 +484,15 @@ static struct pwm_omap_dmtimer_pdata pwm_dmtimer_pdata = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct lirc_rx51_platform_data __maybe_unused rx51_lirc_data = {
|
||||
static struct ir_rx51_platform_data __maybe_unused rx51_ir_data = {
|
||||
.set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
|
||||
};
|
||||
|
||||
static struct platform_device __maybe_unused rx51_lirc_device = {
|
||||
.name = "lirc_rx51",
|
||||
static struct platform_device __maybe_unused rx51_ir_device = {
|
||||
.name = "ir_rx51",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &rx51_lirc_data,
|
||||
.platform_data = &rx51_ir_data,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -533,7 +533,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
|
||||
&omap3_iommu_pdata),
|
||||
OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x4809c000, "4809c000.mmc", &mmc_pdata[0]),
|
||||
OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]),
|
||||
OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data),
|
||||
OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_ir_data),
|
||||
/* Only on am3517 */
|
||||
OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
|
||||
OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
|
||||
@@ -599,7 +599,6 @@ static void pdata_quirks_check(struct pdata_init *quirks)
|
||||
if (of_machine_is_compatible(quirks->compatible)) {
|
||||
if (quirks->fn)
|
||||
quirks->fn();
|
||||
break;
|
||||
}
|
||||
quirks++;
|
||||
}
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/sched/clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
@@ -130,17 +130,16 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
|
||||
freq = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
rcu_read_lock();
|
||||
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
|
||||
if (IS_ERR(opp)) {
|
||||
rcu_read_unlock();
|
||||
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
bootup_volt = dev_pm_opp_get_voltage(opp);
|
||||
rcu_read_unlock();
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (!bootup_volt) {
|
||||
pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
|
||||
Reference in New Issue
Block a user