Merge branch 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: (39 commits) SH: static should be at beginning of declaration sh: move CLKDEV_xxx_ID macro to sh_clk.h sh: clock-shx3: add CLKDEV_ICK_ID for cleanup sh: clock-sh7786: add CLKDEV_ICK_ID for cleanup sh: clock-sh7785: add CLKDEV_ICK_ID for cleanup sh: clock-sh7757: add CLKDEV_ICK_ID for cleanup sh: clock-sh7366: add CLKDEV_ICK_ID for cleanup sh: clock-sh7343: add CLKDEV_ICK_ID for cleanup sh: clock-sh7722: add CLKDEV_ICK_ID for cleanup sh: clock-sh7724: add CLKDEV_ICK_ID for cleanup sh: clock-sh7366: modify I2C clock settings sh: clock-sh7343: modify I2C clock settings sh: clock-sh7723: modify I2C clock settings sh: clock-sh7722: modify I2C clock settings sh: clock-sh7724: modify I2C clock settings serial: sh-sci: Fix up pretty name printing for port IRQs. serial: sh-sci: Kill off per-port enable/disable callbacks. serial: sh-sci: Add missing module description/author bits. serial: sh-sci: Regtype probing doesn't need to be fatal. sh: Tidy up pre-clkdev clk_get() error handling. ...
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@@ -8,6 +8,8 @@
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* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
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*/
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#define SCIx_NOT_SUPPORTED (-1)
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enum {
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SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
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SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
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@@ -25,6 +27,28 @@ enum {
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#define SCSCR_CKE1 (1 << 1)
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#define SCSCR_CKE0 (1 << 0)
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/* SCxSR SCI */
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#define SCI_TDRE 0x80
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#define SCI_RDRF 0x40
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#define SCI_ORER 0x20
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#define SCI_FER 0x10
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#define SCI_PER 0x08
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#define SCI_TEND 0x04
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR SCIF */
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#define SCIF_ER 0x0080
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#define SCIF_TEND 0x0040
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#define SCIF_TDFE 0x0020
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#define SCIF_BRK 0x0010
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#define SCIF_FER 0x0008
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#define SCIF_PER 0x0004
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#define SCIF_RDF 0x0002
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#define SCIF_DR 0x0001
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* Offsets into the sci_port->irqs array */
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enum {
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SCIx_ERI_IRQ,
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@@ -32,6 +56,24 @@ enum {
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SCIx_TXI_IRQ,
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SCIx_BRI_IRQ,
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SCIx_NR_IRQS,
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SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
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};
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enum {
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SCIx_PROBE_REGTYPE,
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SCIx_SCI_REGTYPE,
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SCIx_IRDA_REGTYPE,
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SCIx_SCIFA_REGTYPE,
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SCIx_SCIFB_REGTYPE,
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SCIx_SH3_SCIF_REGTYPE,
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SCIx_SH4_SCIF_REGTYPE,
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SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
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SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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SCIx_SH7705_SCIF_REGTYPE,
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SCIx_NR_REGTYPES,
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};
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#define SCIx_IRQ_MUXED(irq) \
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@@ -42,8 +84,29 @@ enum {
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[SCIx_BRI_IRQ] = (irq), \
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}
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#define SCIx_IRQ_IS_MUXED(port) \
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((port)->cfg->irqs[SCIx_ERI_IRQ] == \
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(port)->cfg->irqs[SCIx_RXI_IRQ]) || \
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((port)->cfg->irqs[SCIx_ERI_IRQ] && \
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!(port)->cfg->irqs[SCIx_RXI_IRQ])
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/*
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* SCI register subset common for all port types.
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, SCBRR, SCSCR, SCxSR,
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SCFCR, SCFDR, SCxTDR, SCxRDR,
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SCLSR, SCTFDR, SCRFDR, SCSPTR,
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SCIx_NR_REGS,
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};
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struct device;
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struct plat_sci_port_ops {
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void (*init_pins)(struct uart_port *, unsigned int cflag);
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};
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/*
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* Platform device specific platform_data struct
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*/
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@@ -56,6 +119,18 @@ struct plat_sci_port {
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unsigned int scbrr_algo_id; /* SCBRR calculation algo */
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unsigned int scscr; /* SCSCR initialization */
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/*
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* Platform overrides if necessary, defaults otherwise.
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*/
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int overrun_bit;
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unsigned int error_mask;
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int port_reg;
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unsigned char regshift;
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unsigned char regtype;
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struct plat_sci_port_ops *ops;
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struct device *dma_dev;
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unsigned int dma_slave_tx;
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@@ -147,4 +147,8 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
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int sh_clk_div6_register(struct clk *clks, int nr);
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int sh_clk_div6_reparent_register(struct clk *clks, int nr);
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
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#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
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#endif /* __SH_CLOCK_H */
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@@ -62,6 +62,12 @@ struct sh_dmae_pdata {
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const unsigned int *ts_shift;
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int ts_shift_num;
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u16 dmaor_init;
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unsigned int chcr_offset;
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u32 chcr_ie_bit;
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unsigned int dmaor_is_32bit:1;
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unsigned int needs_tend_set:1;
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unsigned int no_dmars:1;
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};
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/* DMA register */
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@@ -71,6 +77,8 @@ struct sh_dmae_pdata {
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#define CHCR 0x0C
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#define DMAOR 0x40
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#define TEND 0x18 /* USB-DMAC */
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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