Merge branch 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x

* 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: (39 commits)
  SH: static should be at beginning of declaration
  sh: move CLKDEV_xxx_ID macro to sh_clk.h
  sh: clock-shx3: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7786: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7785: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7757: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7366: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7343: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7722: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7724: add CLKDEV_ICK_ID for cleanup
  sh: clock-sh7366: modify I2C clock settings
  sh: clock-sh7343: modify I2C clock settings
  sh: clock-sh7723: modify I2C clock settings
  sh: clock-sh7722: modify I2C clock settings
  sh: clock-sh7724: modify I2C clock settings
  serial: sh-sci: Fix up pretty name printing for port IRQs.
  serial: sh-sci: Kill off per-port enable/disable callbacks.
  serial: sh-sci: Add missing module description/author bits.
  serial: sh-sci: Regtype probing doesn't need to be fatal.
  sh: Tidy up pre-clkdev clk_get() error handling.
  ...
This commit is contained in:
Linus Torvalds
2011-08-01 06:10:16 -10:00
54 changed files with 966 additions and 1192 deletions

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@@ -8,6 +8,8 @@
* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
*/
#define SCIx_NOT_SUPPORTED (-1)
enum {
SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
@@ -25,6 +27,28 @@ enum {
#define SCSCR_CKE1 (1 << 1)
#define SCSCR_CKE0 (1 << 0)
/* SCxSR SCI */
#define SCI_TDRE 0x80
#define SCI_RDRF 0x40
#define SCI_ORER 0x20
#define SCI_FER 0x10
#define SCI_PER 0x08
#define SCI_TEND 0x04
#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
/* SCxSR SCIF */
#define SCIF_ER 0x0080
#define SCIF_TEND 0x0040
#define SCIF_TDFE 0x0020
#define SCIF_BRK 0x0010
#define SCIF_FER 0x0008
#define SCIF_PER 0x0004
#define SCIF_RDF 0x0002
#define SCIF_DR 0x0001
#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
@@ -32,6 +56,24 @@ enum {
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
SCIx_NR_IRQS,
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
};
enum {
SCIx_PROBE_REGTYPE,
SCIx_SCI_REGTYPE,
SCIx_IRDA_REGTYPE,
SCIx_SCIFA_REGTYPE,
SCIx_SCIFB_REGTYPE,
SCIx_SH3_SCIF_REGTYPE,
SCIx_SH4_SCIF_REGTYPE,
SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
SCIx_SH4_SCIF_FIFODATA_REGTYPE,
SCIx_SH7705_SCIF_REGTYPE,
SCIx_NR_REGTYPES,
};
#define SCIx_IRQ_MUXED(irq) \
@@ -42,8 +84,29 @@ enum {
[SCIx_BRI_IRQ] = (irq), \
}
#define SCIx_IRQ_IS_MUXED(port) \
((port)->cfg->irqs[SCIx_ERI_IRQ] == \
(port)->cfg->irqs[SCIx_RXI_IRQ]) || \
((port)->cfg->irqs[SCIx_ERI_IRQ] && \
!(port)->cfg->irqs[SCIx_RXI_IRQ])
/*
* SCI register subset common for all port types.
* Not all registers will exist on all parts.
*/
enum {
SCSMR, SCBRR, SCSCR, SCxSR,
SCFCR, SCFDR, SCxTDR, SCxRDR,
SCLSR, SCTFDR, SCRFDR, SCSPTR,
SCIx_NR_REGS,
};
struct device;
struct plat_sci_port_ops {
void (*init_pins)(struct uart_port *, unsigned int cflag);
};
/*
* Platform device specific platform_data struct
*/
@@ -56,6 +119,18 @@ struct plat_sci_port {
unsigned int scbrr_algo_id; /* SCBRR calculation algo */
unsigned int scscr; /* SCSCR initialization */
/*
* Platform overrides if necessary, defaults otherwise.
*/
int overrun_bit;
unsigned int error_mask;
int port_reg;
unsigned char regshift;
unsigned char regtype;
struct plat_sci_port_ops *ops;
struct device *dma_dev;
unsigned int dma_slave_tx;

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@@ -147,4 +147,8 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
#endif /* __SH_CLOCK_H */

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@@ -62,6 +62,12 @@ struct sh_dmae_pdata {
const unsigned int *ts_shift;
int ts_shift_num;
u16 dmaor_init;
unsigned int chcr_offset;
u32 chcr_ie_bit;
unsigned int dmaor_is_32bit:1;
unsigned int needs_tend_set:1;
unsigned int no_dmars:1;
};
/* DMA register */
@@ -71,6 +77,8 @@ struct sh_dmae_pdata {
#define CHCR 0x0C
#define DMAOR 0x40
#define TEND 0x18 /* USB-DMAC */
/* DMAOR definitions */
#define DMAOR_AE 0x00000004
#define DMAOR_NMIF 0x00000002