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ARM: tegra: apalis-tk1: reorder cpu dfll clock properties

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Reorder CPU DFLL clock properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Marcel Ziswiler
2018-09-01 15:04:57 +02:00
committed by Thierry Reding
parent a052d2b67f
commit e0cffa9a1b
2 changed files with 2 additions and 2 deletions
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2
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
View File

@@ -1925,8 +1925,8 @@
/* CPU DFLL clock */
clock@70110000 {
status = "okay";
vdd-cpu-supply = <&reg_vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
vdd-cpu-supply = <&reg_vdd_cpu>;
};
ahub@70300000 {

2
arch/arm/boot/dts/tegra124-apalis.dtsi
View File

@@ -1954,8 +1954,8 @@
/* CPU DFLL clock */
clock@70110000 {
status = "okay";
vdd-cpu-supply = <&reg_vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
vdd-cpu-supply = <&reg_vdd_cpu>;
};
ahub@70300000 {