x86/tlb_info: get last level TLB entry number of CPU
For 4KB pages, x86 CPU has 2 or 1 level TLB, first level is data TLB and instruction TLB, second level is shared TLB for both data and instructions. For hupe page TLB, usually there is just one level and seperated by 2MB/4MB and 1GB. Although each levels TLB size is important for performance tuning, but for genernal and rude optimizing, last level TLB entry number is suitable. And in fact, last level TLB always has the biggest entry number. This patch will get the biggest TLB entry number and use it in furture TLB optimizing. Accroding Borislav's suggestion, except tlb_ll[i/d]_* array, other function and data will be released after system boot up. For all kinds of x86 vendor friendly, vendor specific code was moved to its specific files. Signed-off-by: Alex Shi <alex.shi@intel.com> Link: http://lkml.kernel.org/r/1340845344-27557-2-git-send-email-alex.shi@intel.com Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@@ -452,6 +452,25 @@ void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
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c->x86_cache_size = l2size;
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}
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u16 __read_mostly tlb_lli_4k[NR_INFO];
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u16 __read_mostly tlb_lli_2m[NR_INFO];
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u16 __read_mostly tlb_lli_4m[NR_INFO];
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u16 __read_mostly tlb_lld_4k[NR_INFO];
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u16 __read_mostly tlb_lld_2m[NR_INFO];
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u16 __read_mostly tlb_lld_4m[NR_INFO];
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void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c)
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{
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if (this_cpu->c_detect_tlb)
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this_cpu->c_detect_tlb(c);
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printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
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"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
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tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
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tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
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tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES]);
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}
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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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@@ -911,6 +930,8 @@ void __init identify_boot_cpu(void)
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#else
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vgetcpu_set_mode();
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#endif
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if (boot_cpu_data.cpuid_level >= 2)
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cpu_detect_tlb(&boot_cpu_data);
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}
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void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
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