Merge branch 'kvm-arm-for-3.10' of git://github.com/columbia/linux-kvm-arm into queue
* 'kvm-arm-for-3.10' of git://github.com/columbia/linux-kvm-arm: ARM: KVM: iterate over all CPUs for CPU compatibility check KVM: ARM: Fix spelling in error message ARM: KVM: define KVM_ARM_MAX_VCPUS unconditionally KVM: ARM: Fix API documentation for ONE_REG encoding ARM: KVM: promote vfp_host pointer to generic host cpu context ARM: KVM: add architecture specific hook for capabilities ARM: KVM: perform HYP initilization for hotplugged CPUs ARM: KVM: switch to a dual-step HYP init code ARM: KVM: rework HYP page table freeing ARM: KVM: enforce maximum size for identity mapped code ARM: KVM: move to a KVM provided HYP idmap ARM: KVM: fix HYP mapping limitations around zero ARM: KVM: simplify HYP mapping population ARM: KVM: arch_timer: use symbolic constants ARM: KVM: add support for minimal host vs guest profiling
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@@ -1814,22 +1814,22 @@ ARM registers are mapped using the lower 32 bits. The upper 16 of that
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is the register group type, or coprocessor number:
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ARM core registers have the following id bit patterns:
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0x4002 0000 0010 <index into the kvm_regs struct:16>
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0x4020 0000 0010 <index into the kvm_regs struct:16>
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ARM 32-bit CP15 registers have the following id bit patterns:
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0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
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0x4020 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
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ARM 64-bit CP15 registers have the following id bit patterns:
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0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
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0x4030 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
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ARM CCSIDR registers are demultiplexed by CSSELR value:
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0x4002 0000 0011 00 <csselr:8>
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0x4020 0000 0011 00 <csselr:8>
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ARM 32-bit VFP control registers have the following id bit patterns:
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0x4002 0000 0012 1 <regno:12>
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0x4020 0000 0012 1 <regno:12>
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ARM 64-bit FP registers have the following id bit patterns:
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0x4002 0000 0012 0 <regno:12>
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0x4030 0000 0012 0 <regno:12>
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4.69 KVM_GET_ONE_REG
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