Merge tag 'mfd-for-linus-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"Core Frameworks:
- Add new !TOUCHSCREEN_SUN4I dependency for SUN4I_GPADC
- List include/dt-bindings/mfd/* to files supported in MAINTAINERS
New Drivers:
- Intel Apollo Lake SPI NOR
- ST STM32 Timers (Advanced, Basic and PWM)
- Motorola 6556002 CPCAP (PMIC)
New Device Support:
- Add support for AXP221 to axp20x
- Add support for Intel Gemini Lake to intel-lpss-pci
- Add support for MT6323 LED to mt6397-core
- Add support for COMe-bBD#, COMe-bSL6, COMe-bKL6, COMe-cAL6 and
COMe-cKL6 to kempld-core
New Functionality:
- Add support for Analog CODAC to sun6i-prcm
- Add support for Watchdog to lpc_ich
Fix-ups:
- Error handling improvements; axp288_charger, axp20x, ab8500-sysctrl
- Adapt platform data handling; axp20x
- IRQ handling improvements; arizona, axp20x
- Remove superfluous code; arizona, axp20x, lpc_ich
- Trivial coding style/spelling fixes; axp20x, abx500, mfd.txt
- Regmap fix-ups; axp20x
- DT changes; mfd.txt, aspeed-lpc, aspeed-gfx, ab8500-core, tps65912,
mt6397
- Use new I2C probing mechanism; max77686
- Constification; rk808
Bug Fixes:
- Stop data transfer whilst suspended; cros_ec"
* tag 'mfd-for-linus-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (43 commits)
mfd: lpc_ich: Enable watchdog on Intel Apollo Lake PCH
mfd: lpc_ich: Remove useless comments in core part
mfd: Add support for several boards to Kontron PLD driver
mfd: constify regmap_irq_chip structures
MAINTAINERS: Add include/dt-bindings/mfd to MFD entry
mfd: cpcap: Add minimal support
mfd: mt6397: Add MT6323 LED support into MT6397 driver
Documentation: devicetree: Add LED subnode binding for MT6323 PMIC
mfd: tps65912: Export OF device ID table as module aliases
mfd: ab8500-core: Rename clock device and compatible
mfd: cros_ec: Send correct suspend/resume event to EC
mfd: max77686: Remove I2C device ID table
mfd: max77686: Use the struct i2c_driver .probe_new instead of .probe
mfd: max77686: Use of_device_get_match_data() helper
mfd: max77686: Don't attempt to get i2c_device_id .data
mfd: ab8500-sysctrl: Handle probe deferral
mfd: intel-lpss: Add Intel Gemini Lake PCI IDs
mfd: axp20x: Fix AXP806 access errors on cold boot
mfd: cros_ec: Send suspend state notification to EC
mfd: cros_ec: Prevent data transfer while device is suspended
...
This commit is contained in:
Linus Torvalds
@@ -45,7 +45,7 @@ enum abx500_adc_therm {
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* struct abx500_res_to_temp - defines one point in a temp to res curve. To
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* be used in battery packs that combines the identification resistor with a
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* NTC resistor.
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* @temp: battery pack temperature in Celcius
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* @temp: battery pack temperature in Celsius
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* @resist: NTC resistor net total resistance
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*/
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struct abx500_res_to_temp {
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@@ -279,7 +279,7 @@ enum bup_vch_sel {
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* struct res_to_temp - defines one point in a temp to res curve. To
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* be used in battery packs that combines the identification resistor with a
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* NTC resistor.
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* @temp: battery pack temperature in Celcius
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* @temp: battery pack temperature in Celsius
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* @resist: NTC resistor net total resistance
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*/
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struct res_to_temp {
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@@ -290,7 +290,7 @@ struct res_to_temp {
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/**
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* struct batres_vs_temp - defines one point in a temp vs battery internal
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* resistance curve.
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* @temp: battery pack temperature in Celcius
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* @temp: battery pack temperature in Celsius
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* @resist: battery internal reistance in mOhm
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*/
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struct batres_vs_temp {
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@@ -235,10 +235,20 @@ enum axp20x_variants {
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#define AXP22X_BATLOW_THRES1 0xe6
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/* AXP288 specific registers */
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#define AXP288_POWER_REASON 0x02
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#define AXP288_BC_GLOBAL 0x2c
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#define AXP288_BC_VBUS_CNTL 0x2d
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#define AXP288_BC_USB_STAT 0x2e
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#define AXP288_BC_DET_STAT 0x2f
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#define AXP288_PMIC_ADC_H 0x56
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#define AXP288_PMIC_ADC_L 0x57
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#define AXP288_TS_ADC_H 0x58
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#define AXP288_TS_ADC_L 0x59
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#define AXP288_GP_ADC_H 0x5a
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#define AXP288_GP_ADC_L 0x5b
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#define AXP288_ADC_TS_PIN_CTRL 0x84
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#define AXP288_PMIC_ADC_EN 0x84
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#define AXP288_RT_BATT_V_H 0xa0
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#define AXP288_RT_BATT_V_L 0xa1
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/* Fuel Gauge */
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#define AXP288_FG_RDC1_REG 0xba
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@@ -515,14 +525,10 @@ enum axp809_irqs {
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AXP809_IRQ_GPIO0_INPUT,
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};
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#define AXP288_TS_ADC_H 0x58
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#define AXP288_TS_ADC_L 0x59
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#define AXP288_GP_ADC_H 0x5a
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#define AXP288_GP_ADC_L 0x5b
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struct axp20x_dev {
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struct device *dev;
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int irq;
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unsigned long irq_flags;
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struct regmap *regmap;
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struct regmap_irq_chip_data *regmap_irqc;
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long variant;
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@@ -582,7 +588,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x);
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int axp20x_device_probe(struct axp20x_dev *axp20x);
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/**
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* axp20x_device_probe(): Remove a axp20x device
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* axp20x_device_remove(): Remove a axp20x device
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*
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* @axp20x: axp20x device to remove
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*
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@@ -103,6 +103,7 @@ struct cros_ec_command {
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* @din_size: size of din buffer to allocate (zero to use static din)
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* @dout_size: size of dout buffer to allocate (zero to use static dout)
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* @wake_enabled: true if this device can wake the system from sleep
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* @suspended: true if this device had been suspended
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* @cmd_xfer: send command to EC and get response
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* Returns the number of bytes received if the communication succeeded, but
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* that doesn't mean the EC was happy with the command. The caller
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@@ -136,6 +137,7 @@ struct cros_ec_device {
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int din_size;
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int dout_size;
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bool wake_enabled;
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bool suspended;
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int (*cmd_xfer)(struct cros_ec_device *ec,
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struct cros_ec_command *msg);
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int (*pkt_xfer)(struct cros_ec_device *ec,
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@@ -1840,18 +1840,69 @@ struct ec_response_tmp006_get_raw {
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*
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* Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
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* expected response size.
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*
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* NOTE: This has been superseded by EC_CMD_MKBP_GET_NEXT_EVENT. If you wish
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* to obtain the instantaneous state, use EC_CMD_MKBP_INFO with the type
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* EC_MKBP_INFO_CURRENT and event EC_MKBP_EVENT_KEY_MATRIX.
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*/
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#define EC_CMD_MKBP_STATE 0x60
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/* Provide information about the matrix : number of rows and columns */
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/*
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* Provide information about various MKBP things. See enum ec_mkbp_info_type.
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*/
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#define EC_CMD_MKBP_INFO 0x61
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struct ec_response_mkbp_info {
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uint32_t rows;
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uint32_t cols;
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uint8_t switches;
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/* Formerly "switches", which was 0. */
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uint8_t reserved;
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} __packed;
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struct ec_params_mkbp_info {
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uint8_t info_type;
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uint8_t event_type;
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} __packed;
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enum ec_mkbp_info_type {
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/*
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* Info about the keyboard matrix: number of rows and columns.
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*
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* Returns struct ec_response_mkbp_info.
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*/
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EC_MKBP_INFO_KBD = 0,
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/*
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* For buttons and switches, info about which specifically are
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* supported. event_type must be set to one of the values in enum
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* ec_mkbp_event.
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*
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* For EC_MKBP_EVENT_BUTTON and EC_MKBP_EVENT_SWITCH, returns a 4 byte
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* bitmask indicating which buttons or switches are present. See the
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* bit inidices below.
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*/
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EC_MKBP_INFO_SUPPORTED = 1,
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/*
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* Instantaneous state of buttons and switches.
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*
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* event_type must be set to one of the values in enum ec_mkbp_event.
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*
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* For EC_MKBP_EVENT_KEY_MATRIX, returns uint8_t key_matrix[13]
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* indicating the current state of the keyboard matrix.
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*
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* For EC_MKBP_EVENT_HOST_EVENT, return uint32_t host_event, the raw
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* event state.
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*
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* For EC_MKBP_EVENT_BUTTON, returns uint32_t buttons, indicating the
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* state of supported buttons.
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*
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* For EC_MKBP_EVENT_SWITCH, returns uint32_t switches, indicating the
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* state of supported switches.
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*/
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EC_MKBP_INFO_CURRENT = 2,
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};
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/* Simulate key press */
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#define EC_CMD_MKBP_SIMULATE_KEY 0x62
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@@ -1984,6 +2035,12 @@ enum ec_mkbp_event {
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/* New Sensor FIFO data. The event data is fifo_info structure. */
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EC_MKBP_EVENT_SENSOR_FIFO = 2,
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/* The state of the non-matrixed buttons have changed. */
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EC_MKBP_EVENT_BUTTON = 3,
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/* The state of the switches have changed. */
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EC_MKBP_EVENT_SWITCH = 4,
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/* Number of MKBP events */
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EC_MKBP_EVENT_COUNT,
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};
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@@ -1993,6 +2050,9 @@ union ec_response_get_next_data {
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/* Unaligned */
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uint32_t host_event;
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uint32_t buttons;
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uint32_t switches;
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} __packed;
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struct ec_response_get_next_event {
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@@ -2001,6 +2061,16 @@ struct ec_response_get_next_event {
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union ec_response_get_next_data data;
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} __packed;
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/* Bit indices for buttons and switches.*/
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/* Buttons */
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#define EC_MKBP_POWER_BUTTON 0
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#define EC_MKBP_VOL_UP 1
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#define EC_MKBP_VOL_DOWN 2
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/* Switches */
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#define EC_MKBP_LID_OPEN 0
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#define EC_MKBP_TABLET_MODE 1
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/*****************************************************************************/
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/* Temperature sensor commands */
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@@ -2478,6 +2548,20 @@ struct ec_params_ext_power_current_limit {
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uint32_t limit; /* in mA */
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} __packed;
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/* Inform the EC when entering a sleep state */
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#define EC_CMD_HOST_SLEEP_EVENT 0xa9
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enum host_sleep_event {
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HOST_SLEEP_EVENT_S3_SUSPEND = 1,
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HOST_SLEEP_EVENT_S3_RESUME = 2,
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HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
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HOST_SLEEP_EVENT_S0IX_RESUME = 4
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};
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struct ec_params_host_sleep_event {
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uint8_t sleep_event;
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} __packed;
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/*****************************************************************************/
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/* Smart battery pass-through */
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292
include/linux/mfd/motorola-cpcap.h
Normal file
292
include/linux/mfd/motorola-cpcap.h
Normal file
@@ -0,0 +1,292 @@
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/*
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* The register defines are based on earlier cpcap.h in Motorola Linux kernel
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* tree.
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*
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* Copyright (C) 2007-2009 Motorola, Inc.
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*
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* Rewritten for the real register offsets instead of enumeration
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* to make the defines usable with Linux kernel regmap support
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*
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* Copyright (C) 2016 Tony Lindgren <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define CPCAP_VENDOR_ST 0
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#define CPCAP_VENDOR_TI 1
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#define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1)
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#define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
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#define CPCAP_REVISION_1_0 0x08
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#define CPCAP_REVISION_1_1 0x09
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#define CPCAP_REVISION_2_0 0x10
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#define CPCAP_REVISION_2_1 0x11
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/* CPCAP registers */
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#define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
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#define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
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#define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
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#define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
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#define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
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#define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
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#define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
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#define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
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#define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */
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#define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */
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#define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */
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#define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */
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#define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */
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#define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */
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#define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */
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#define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */
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#define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */
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#define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */
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#define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
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#define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */
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#define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */
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#define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */
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#define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */
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#define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */
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#define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */
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#define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */
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#define CPCAP_REG_PC1 0x021c /* Power Cut 1 */
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#define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */
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#define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */
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#define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */
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#define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */
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#define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */
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#define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */
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#define CPCAP_REG_PF 0x0238 /* Print Format */
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#define CPCAP_REG_SCC 0x0400 /* System Clock Control */
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#define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */
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#define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */
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#define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */
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#define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */
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#define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */
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#define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */
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#define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */
|
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#define CPCAP_REG_DAY 0x0420 /* Day */
|
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#define CPCAP_REG_DAYA 0x0424 /* Day Alarm */
|
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#define CPCAP_REG_VAL1 0x0428 /* Validity 1 */
|
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#define CPCAP_REG_VAL2 0x042c /* Validity 2 */
|
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|
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#define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */
|
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#define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */
|
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#define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */
|
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#define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */
|
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#define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */
|
||||
#define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */
|
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#define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */
|
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#define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */
|
||||
#define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */
|
||||
#define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */
|
||||
#define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */
|
||||
#define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */
|
||||
#define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */
|
||||
#define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */
|
||||
#define CPCAP_REG_VDACC 0x0638 /* VDAC Control */
|
||||
#define CPCAP_REG_VDIGC 0x063c /* VDIG Control */
|
||||
#define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */
|
||||
#define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */
|
||||
#define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */
|
||||
#define CPCAP_REG_VPLLC 0x064c /* VPLL Control */
|
||||
#define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */
|
||||
#define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */
|
||||
#define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */
|
||||
#define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */
|
||||
#define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */
|
||||
#define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */
|
||||
#define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */
|
||||
#define CPCAP_REG_VUSBC 0x066c /* VUSB Control */
|
||||
#define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */
|
||||
#define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */
|
||||
#define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */
|
||||
#define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */
|
||||
#define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */
|
||||
|
||||
#define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */
|
||||
#define CPCAP_REG_CC 0x0804 /* Codec Control */
|
||||
#define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */
|
||||
#define CPCAP_REG_SDAC 0x080c /* Stereo DAC */
|
||||
#define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */
|
||||
#define CPCAP_REG_TXI 0x0814 /* TX Inputs */
|
||||
#define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */
|
||||
#define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */
|
||||
#define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */
|
||||
#define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */
|
||||
#define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */
|
||||
#define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */
|
||||
#define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */
|
||||
#define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */
|
||||
#define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */
|
||||
#define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */
|
||||
#define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */
|
||||
#define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */
|
||||
|
||||
#define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */
|
||||
#define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */
|
||||
#define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */
|
||||
#define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */
|
||||
#define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */
|
||||
#define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */
|
||||
#define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */
|
||||
#define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */
|
||||
#define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */
|
||||
#define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */
|
||||
|
||||
#define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */
|
||||
#define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */
|
||||
#define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */
|
||||
#define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */
|
||||
#define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */
|
||||
#define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */
|
||||
#define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */
|
||||
#define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */
|
||||
#define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */
|
||||
#define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */
|
||||
#define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */
|
||||
#define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */
|
||||
|
||||
#define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */
|
||||
#define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */
|
||||
#define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */
|
||||
#define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */
|
||||
#define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */
|
||||
#define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */
|
||||
#define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */
|
||||
#define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */
|
||||
#define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */
|
||||
#define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */
|
||||
#define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */
|
||||
#define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */
|
||||
#define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */
|
||||
#define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */
|
||||
#define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */
|
||||
#define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */
|
||||
#define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */
|
||||
#define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */
|
||||
#define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */
|
||||
#define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */
|
||||
#define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */
|
||||
#define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */
|
||||
#define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */
|
||||
#define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */
|
||||
#define CPCAP_REG_USBD 0x0e60 /* USB Debug */
|
||||
#define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */
|
||||
#define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */
|
||||
#define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */
|
||||
|
||||
#define CPCAP_REG_VMC 0x0eac /* Video Mux Control */
|
||||
#define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */
|
||||
#define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */
|
||||
|
||||
#define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */
|
||||
|
||||
#define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */
|
||||
|
||||
#define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */
|
||||
|
||||
#define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */
|
||||
|
||||
#define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */
|
||||
|
||||
#define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */
|
||||
|
||||
#define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */
|
||||
#define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */
|
||||
#define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */
|
||||
#define CPCAP_REG_REDC 0x100c /* Red Triode Control */
|
||||
#define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */
|
||||
#define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */
|
||||
#define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */
|
||||
#define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */
|
||||
#define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */
|
||||
#define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */
|
||||
|
||||
#define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */
|
||||
#define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */
|
||||
#define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */
|
||||
#define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */
|
||||
|
||||
#define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */
|
||||
|
||||
#define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */
|
||||
#define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */
|
||||
#define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */
|
||||
#define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */
|
||||
|
||||
#define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */
|
||||
|
||||
#define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */
|
||||
#define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */
|
||||
#define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */
|
||||
#define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */
|
||||
|
||||
#define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */
|
||||
#define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */
|
||||
#define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */
|
||||
#define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */
|
||||
#define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */
|
||||
#define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */
|
||||
#define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */
|
||||
#define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */
|
||||
#define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */
|
||||
#define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */
|
||||
#define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */
|
||||
|
||||
#define CPCAP_REG_TEST 0x7c00 /* Test */
|
||||
|
||||
#define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */
|
||||
|
||||
#define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */
|
||||
|
||||
/*
|
||||
* Helpers for child devices to check the revision and vendor.
|
||||
*
|
||||
* REVISIT: No documentation for the bits below, please update
|
||||
* to use proper names for defines when available.
|
||||
*/
|
||||
|
||||
static inline int cpcap_get_revision(struct device *dev,
|
||||
struct regmap *regmap,
|
||||
u16 *revision)
|
||||
{
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(regmap, CPCAP_REG_VERSC1, &val);
|
||||
if (ret) {
|
||||
dev_err(dev, "Could not read revision\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
*revision = ((val >> 3) & 0x7) | ((val << 3) & 0x38);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int cpcap_get_vendor(struct device *dev,
|
||||
struct regmap *regmap,
|
||||
u16 *vendor)
|
||||
{
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(regmap, CPCAP_REG_VERSC1, &val);
|
||||
if (ret) {
|
||||
dev_err(dev, "Could not read vendor\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
*vendor = (val >> 6) & 0x7;
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user