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drm: bridge: dw-hdmi: Switch to V4L bus format and encodings

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Switch code to use the newly introduced V4L bus formats IDs instead of custom
defines. Also use the V4L encoding defines.

Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.

Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
2017-04-04 14:31:57 +02:00
parent a23d6265f0
commit def23aa7e9
2 changed files with 297 additions and 98 deletions
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63
include/drm/bridge/dw_hdmi.h
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@@ -14,6 +14,67 @@
struct dw_hdmi;
/**
* DOC: Supported input formats and encodings
*
* Depending on the Hardware configuration of the Controller IP, it supports
* a subset of the following input formats and encodings on its internal
* 48bit bus.
*
* +----------------------+----------------------------------+------------------------------+
* + Format Name + Format Code + Encodings +
* +----------------------+----------------------------------+------------------------------+
* + RGB 4:4:4 8bit + ``MEDIA_BUS_FMT_RGB888_1X24`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
* +----------------------+----------------------------------+------------------------------+
* + RGB 4:4:4 10bits + ``MEDIA_BUS_FMT_RGB101010_1X30`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
* +----------------------+----------------------------------+------------------------------+
* + RGB 4:4:4 12bits + ``MEDIA_BUS_FMT_RGB121212_1X36`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
* +----------------------+----------------------------------+------------------------------+
* + RGB 4:4:4 16bits + ``MEDIA_BUS_FMT_RGB161616_1X48`` + ``V4L2_YCBCR_ENC_DEFAULT`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:4:4 8bit + ``MEDIA_BUS_FMT_YUV8_1X24`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* + + + or ``V4L2_YCBCR_ENC_XV601`` +
* + + + or ``V4L2_YCBCR_ENC_XV709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:4:4 10bits + ``MEDIA_BUS_FMT_YUV10_1X30`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* + + + or ``V4L2_YCBCR_ENC_XV601`` +
* + + + or ``V4L2_YCBCR_ENC_XV709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:4:4 12bits + ``MEDIA_BUS_FMT_YUV12_1X36`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* + + + or ``V4L2_YCBCR_ENC_XV601`` +
* + + + or ``V4L2_YCBCR_ENC_XV709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:4:4 16bits + ``MEDIA_BUS_FMT_YUV16_1X48`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* + + + or ``V4L2_YCBCR_ENC_XV601`` +
* + + + or ``V4L2_YCBCR_ENC_XV709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:2 8bit + ``MEDIA_BUS_FMT_UYVY8_1X16`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:2 10bits + ``MEDIA_BUS_FMT_UYVY10_1X20`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:2 12bits + ``MEDIA_BUS_FMT_UYVY12_1X24`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:0 8bit + ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` + ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:0 10bits + ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``+ ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:0 12bits + ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``+ ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
* + YCbCr 4:2:0 16bits + ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``+ ``V4L2_YCBCR_ENC_601`` +
* + + + or ``V4L2_YCBCR_ENC_709`` +
* +----------------------+----------------------------------+------------------------------+
*/
enum {
DW_HDMI_RES_8,
DW_HDMI_RES_10,
@@ -62,6 +123,8 @@ struct dw_hdmi_plat_data {
struct regmap *regm;
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
struct drm_display_mode *mode);
unsigned long input_bus_format;
unsigned long input_bus_encoding;
/* Vendor PHY support */
const struct dw_hdmi_phy_ops *phy_ops;