drm/tegra: Move driver to DRM tree
In order to make subsystem-wide changes easier, move the Tegra DRM driver back into the DRM tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
225
drivers/gpu/drm/tegra/rgb.c
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225
drivers/gpu/drm/tegra/rgb.c
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/*
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* Copyright (C) 2012 Avionic Design GmbH
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include "drm.h"
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#include "dc.h"
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struct tegra_rgb {
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struct tegra_output output;
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struct clk *clk_parent;
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struct clk *clk;
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};
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static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
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{
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return container_of(output, struct tegra_rgb, output);
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}
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struct reg_entry {
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unsigned long offset;
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unsigned long value;
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};
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static const struct reg_entry rgb_enable[] = {
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{ DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
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{ DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
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{ DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
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};
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static const struct reg_entry rgb_disable[] = {
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{ DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
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{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
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{ DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
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{ DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
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};
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static void tegra_dc_write_regs(struct tegra_dc *dc,
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const struct reg_entry *table,
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unsigned int num)
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{
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unsigned int i;
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for (i = 0; i < num; i++)
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tegra_dc_writel(dc, table[i].value, table[i].offset);
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}
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static int tegra_output_rgb_enable(struct tegra_output *output)
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{
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struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
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tegra_dc_write_regs(dc, rgb_enable, ARRAY_SIZE(rgb_enable));
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return 0;
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}
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static int tegra_output_rgb_disable(struct tegra_output *output)
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{
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struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
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tegra_dc_write_regs(dc, rgb_disable, ARRAY_SIZE(rgb_disable));
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return 0;
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}
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static int tegra_output_rgb_setup_clock(struct tegra_output *output,
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struct clk *clk, unsigned long pclk)
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{
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struct tegra_rgb *rgb = to_rgb(output);
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return clk_set_parent(clk, rgb->clk_parent);
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}
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static int tegra_output_rgb_check_mode(struct tegra_output *output,
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struct drm_display_mode *mode,
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enum drm_mode_status *status)
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{
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/*
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* FIXME: For now, always assume that the mode is okay. There are
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* unresolved issues with clk_round_rate(), which doesn't always
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* reliably report whether a frequency can be set or not.
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*/
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*status = MODE_OK;
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return 0;
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}
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static const struct tegra_output_ops rgb_ops = {
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.enable = tegra_output_rgb_enable,
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.disable = tegra_output_rgb_disable,
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.setup_clock = tegra_output_rgb_setup_clock,
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.check_mode = tegra_output_rgb_check_mode,
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};
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int tegra_dc_rgb_probe(struct tegra_dc *dc)
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{
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struct device_node *np;
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struct tegra_rgb *rgb;
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int err;
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np = of_get_child_by_name(dc->dev->of_node, "rgb");
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if (!np || !of_device_is_available(np))
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return -ENODEV;
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rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
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if (!rgb)
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return -ENOMEM;
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rgb->output.dev = dc->dev;
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rgb->output.of_node = np;
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err = tegra_output_parse_dt(&rgb->output);
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if (err < 0)
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return err;
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rgb->clk = devm_clk_get(dc->dev, NULL);
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if (IS_ERR(rgb->clk)) {
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dev_err(dc->dev, "failed to get clock\n");
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return PTR_ERR(rgb->clk);
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}
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rgb->clk_parent = devm_clk_get(dc->dev, "parent");
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if (IS_ERR(rgb->clk_parent)) {
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dev_err(dc->dev, "failed to get parent clock\n");
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return PTR_ERR(rgb->clk_parent);
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}
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err = clk_set_parent(rgb->clk, rgb->clk_parent);
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if (err < 0) {
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dev_err(dc->dev, "failed to set parent clock: %d\n", err);
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return err;
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}
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dc->rgb = &rgb->output;
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return 0;
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}
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int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
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{
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struct tegra_rgb *rgb = to_rgb(dc->rgb);
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int err;
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if (!dc->rgb)
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return -ENODEV;
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rgb->output.type = TEGRA_OUTPUT_RGB;
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rgb->output.ops = &rgb_ops;
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err = tegra_output_init(dc->base.dev, &rgb->output);
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if (err < 0) {
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dev_err(dc->dev, "output setup failed: %d\n", err);
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return err;
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}
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/*
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* By default, outputs can be associated with each display controller.
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* RGB outputs are an exception, so we make sure they can be attached
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* to only their parent display controller.
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*/
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rgb->output.encoder.possible_crtcs = 1 << dc->pipe;
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return 0;
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}
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int tegra_dc_rgb_exit(struct tegra_dc *dc)
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{
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if (dc->rgb) {
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int err;
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err = tegra_output_disable(dc->rgb);
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if (err < 0) {
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dev_err(dc->dev, "output failed to disable: %d\n", err);
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return err;
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}
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err = tegra_output_exit(dc->rgb);
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if (err < 0) {
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dev_err(dc->dev, "output cleanup failed: %d\n", err);
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return err;
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}
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dc->rgb = NULL;
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}
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return 0;
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}
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