intel: Move the Intel wired LAN drivers
Moves the Intel wired LAN drivers into drivers/net/ethernet/intel/ and the necessary Kconfig and Makefile changes. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Jeff Kirsher
1516
drivers/net/ethernet/intel/e1000e/80003es2lan.c
Normal file
1516
drivers/net/ethernet/intel/e1000e/80003es2lan.c
Normal file
File diff suppressed because it is too large
Load Diff
2115
drivers/net/ethernet/intel/e1000e/82571.c
Normal file
2115
drivers/net/ethernet/intel/e1000e/82571.c
Normal file
File diff suppressed because it is too large
Load Diff
37
drivers/net/ethernet/intel/e1000e/Makefile
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37
drivers/net/ethernet/intel/e1000e/Makefile
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@@ -0,0 +1,37 @@
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################################################################################
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#
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# Intel PRO/1000 Linux driver
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# Copyright(c) 1999 - 2011 Intel Corporation.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program; if not, write to the Free Software Foundation, Inc.,
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# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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#
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# The full GNU General Public License is included in this distribution in
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# the file called "COPYING".
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#
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# Contact Information:
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# Linux NICS <linux.nics@intel.com>
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# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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#
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################################################################################
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#
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# Makefile for the Intel(R) PRO/1000 ethernet driver
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#
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obj-$(CONFIG_E1000E) += e1000e.o
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e1000e-objs := 82571.o ich8lan.o 80003es2lan.o \
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lib.o phy.o param.o ethtool.o netdev.o
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844
drivers/net/ethernet/intel/e1000e/defines.h
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844
drivers/net/ethernet/intel/e1000e/defines.h
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@@ -0,0 +1,844 @@
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/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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more details.
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You should have received a copy of the GNU General Public License along with
|
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this program; if not, write to the Free Software Foundation, Inc.,
|
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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||||
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000_DEFINES_H_
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#define _E1000_DEFINES_H_
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#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
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#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
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#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
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#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
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#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
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#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
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#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
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#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
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#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
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#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
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#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
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#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
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#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
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#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
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#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
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#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
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#define REQ_TX_DESCRIPTOR_MULTIPLE 8
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#define REQ_RX_DESCRIPTOR_MULTIPLE 8
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/* Definitions for power management and wakeup registers */
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/* Wake Up Control */
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#define E1000_WUC_APME 0x00000001 /* APM Enable */
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#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
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#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
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/* Wake Up Filter Control */
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#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
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#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
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#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
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#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
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/* Wake Up Status */
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#define E1000_WUS_LNKC E1000_WUFC_LNKC
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#define E1000_WUS_MAG E1000_WUFC_MAG
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#define E1000_WUS_EX E1000_WUFC_EX
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#define E1000_WUS_MC E1000_WUFC_MC
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#define E1000_WUS_BC E1000_WUFC_BC
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/* Extended Device Control */
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#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
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#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
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#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
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#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
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#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
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#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
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#define E1000_CTRL_EXT_EIAME 0x01000000
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#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
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#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
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#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
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#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
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#define E1000_CTRL_EXT_LSECCK 0x00001000
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#define E1000_CTRL_EXT_PHYPDEN 0x00100000
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/* Receive Descriptor bit definitions */
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#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
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#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
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#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
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#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
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#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
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#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
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#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
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#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
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#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
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#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
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#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
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#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
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#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
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#define E1000_RXDEXT_STATERR_CE 0x01000000
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#define E1000_RXDEXT_STATERR_SE 0x02000000
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#define E1000_RXDEXT_STATERR_SEQ 0x04000000
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#define E1000_RXDEXT_STATERR_CXE 0x10000000
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#define E1000_RXDEXT_STATERR_RXE 0x80000000
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/* mask to determine if packets should be dropped due to frame errors */
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#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
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E1000_RXD_ERR_CE | \
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E1000_RXD_ERR_SE | \
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E1000_RXD_ERR_SEQ | \
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E1000_RXD_ERR_CXE | \
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E1000_RXD_ERR_RXE)
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/* Same mask, but for extended and packet split descriptors */
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#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
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E1000_RXDEXT_STATERR_CE | \
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E1000_RXDEXT_STATERR_SE | \
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E1000_RXDEXT_STATERR_SEQ | \
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E1000_RXDEXT_STATERR_CXE | \
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E1000_RXDEXT_STATERR_RXE)
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#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
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/* Management Control */
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#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
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#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
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#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
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#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
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#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
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/* Enable MAC address filtering */
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#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
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/* Enable MNG packets to host memory */
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#define E1000_MANC_EN_MNG2HOST 0x00200000
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#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
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#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
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#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
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#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
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/* Receive Control */
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#define E1000_RCTL_EN 0x00000002 /* enable */
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#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
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#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
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#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
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#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
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#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
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#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
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#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
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#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
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#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
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#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
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#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
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#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
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#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
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#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
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#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
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#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
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#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
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#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
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#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
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#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
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#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
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#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
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#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
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#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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/*
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* Use byte values for the following shift parameters
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* Usage:
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* psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
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* E1000_PSRCTL_BSIZE0_MASK) |
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* ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
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* E1000_PSRCTL_BSIZE1_MASK) |
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* ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
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* E1000_PSRCTL_BSIZE2_MASK) |
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* ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
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* E1000_PSRCTL_BSIZE3_MASK))
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* where value0 = [128..16256], default=256
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* value1 = [1024..64512], default=4096
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* value2 = [0..64512], default=4096
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* value3 = [0..64512], default=0
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*/
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#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
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#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
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#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
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#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
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#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
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#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
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#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
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#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
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/* SWFW_SYNC Definitions */
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#define E1000_SWFW_EEP_SM 0x1
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#define E1000_SWFW_PHY0_SM 0x2
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#define E1000_SWFW_PHY1_SM 0x4
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#define E1000_SWFW_CSR_SM 0x8
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/* Device Control */
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#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
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#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
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#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
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#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
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#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
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#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
|
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#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
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#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
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#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
|
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#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
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#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
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#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
|
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#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
|
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#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
|
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#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
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#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
|
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#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
|
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#define E1000_CTRL_RST 0x04000000 /* Global reset */
|
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#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
|
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#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
|
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#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
|
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#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
|
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|
||||
/*
|
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* Bit definitions for the Management Data IO (MDIO) and Management Data
|
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* Clock (MDC) pins in the Device Control Register.
|
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*/
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/* Device Status */
|
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#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
|
||||
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
|
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#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
|
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#define E1000_STATUS_FUNC_SHIFT 2
|
||||
#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
|
||||
#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
|
||||
#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
|
||||
#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
|
||||
#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
|
||||
#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
|
||||
#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
|
||||
#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
|
||||
|
||||
/* Constants used to interpret the masked PCI-X bus speed. */
|
||||
|
||||
#define HALF_DUPLEX 1
|
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#define FULL_DUPLEX 2
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||||
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#define ADVERTISE_10_HALF 0x0001
|
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#define ADVERTISE_10_FULL 0x0002
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#define ADVERTISE_100_HALF 0x0004
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#define ADVERTISE_100_FULL 0x0008
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#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
|
||||
#define ADVERTISE_1000_FULL 0x0020
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||||
|
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/* 1000/H is not supported, nor spec-compliant. */
|
||||
#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
|
||||
ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
|
||||
ADVERTISE_1000_FULL)
|
||||
#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
|
||||
ADVERTISE_100_HALF | ADVERTISE_100_FULL)
|
||||
#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
|
||||
#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
|
||||
#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
|
||||
|
||||
#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
|
||||
|
||||
/* LED Control */
|
||||
#define E1000_PHY_LED0_MODE_MASK 0x00000007
|
||||
#define E1000_PHY_LED0_IVRT 0x00000008
|
||||
#define E1000_PHY_LED0_MASK 0x0000001F
|
||||
|
||||
#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
|
||||
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
|
||||
#define E1000_LEDCTL_LED0_IVRT 0x00000040
|
||||
#define E1000_LEDCTL_LED0_BLINK 0x00000080
|
||||
|
||||
#define E1000_LEDCTL_MODE_LINK_UP 0x2
|
||||
#define E1000_LEDCTL_MODE_LED_ON 0xE
|
||||
#define E1000_LEDCTL_MODE_LED_OFF 0xF
|
||||
|
||||
/* Transmit Descriptor bit definitions */
|
||||
#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
|
||||
#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
|
||||
#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
|
||||
#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
|
||||
#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
||||
#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
|
||||
#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
|
||||
#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
|
||||
#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
|
||||
#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
|
||||
#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
|
||||
#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
|
||||
#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
|
||||
#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
|
||||
#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
|
||||
#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
|
||||
#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
|
||||
#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
|
||||
#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
|
||||
|
||||
/* Transmit Control */
|
||||
#define E1000_TCTL_EN 0x00000002 /* enable Tx */
|
||||
#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
|
||||
#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
|
||||
#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
|
||||
#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
|
||||
#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
|
||||
|
||||
/* Transmit Arbitration Count */
|
||||
|
||||
/* SerDes Control */
|
||||
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
|
||||
|
||||
/* Receive Checksum Control */
|
||||
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
|
||||
#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
|
||||
|
||||
/* Header split receive */
|
||||
#define E1000_RFCTL_NFSW_DIS 0x00000040
|
||||
#define E1000_RFCTL_NFSR_DIS 0x00000080
|
||||
#define E1000_RFCTL_ACK_DIS 0x00001000
|
||||
#define E1000_RFCTL_EXTEN 0x00008000
|
||||
#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
|
||||
#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
|
||||
|
||||
/* Collision related configuration parameters */
|
||||
#define E1000_COLLISION_THRESHOLD 15
|
||||
#define E1000_CT_SHIFT 4
|
||||
#define E1000_COLLISION_DISTANCE 63
|
||||
#define E1000_COLD_SHIFT 12
|
||||
|
||||
/* Default values for the transmit IPG register */
|
||||
#define DEFAULT_82543_TIPG_IPGT_COPPER 8
|
||||
|
||||
#define E1000_TIPG_IPGT_MASK 0x000003FF
|
||||
|
||||
#define DEFAULT_82543_TIPG_IPGR1 8
|
||||
#define E1000_TIPG_IPGR1_SHIFT 10
|
||||
|
||||
#define DEFAULT_82543_TIPG_IPGR2 6
|
||||
#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
|
||||
#define E1000_TIPG_IPGR2_SHIFT 20
|
||||
|
||||
#define MAX_JUMBO_FRAME_SIZE 0x3F00
|
||||
|
||||
/* Extended Configuration Control and Size */
|
||||
#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
|
||||
#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
|
||||
#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
|
||||
#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
|
||||
#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
|
||||
#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
|
||||
#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
|
||||
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
|
||||
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
|
||||
|
||||
#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
|
||||
#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
|
||||
#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
|
||||
#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
|
||||
|
||||
#define E1000_KABGTXD_BGSQLBIAS 0x00050000
|
||||
|
||||
/* PBA constants */
|
||||
#define E1000_PBA_8K 0x0008 /* 8KB */
|
||||
#define E1000_PBA_16K 0x0010 /* 16KB */
|
||||
|
||||
#define E1000_PBS_16K E1000_PBA_16K
|
||||
|
||||
#define IFS_MAX 80
|
||||
#define IFS_MIN 40
|
||||
#define IFS_RATIO 4
|
||||
#define IFS_STEP 10
|
||||
#define MIN_NUM_XMITS 1000
|
||||
|
||||
/* SW Semaphore Register */
|
||||
#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
|
||||
#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
|
||||
#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
|
||||
|
||||
#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
|
||||
|
||||
/* Interrupt Cause Read */
|
||||
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
|
||||
#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
|
||||
#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
|
||||
#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
|
||||
#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
|
||||
#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
|
||||
#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
|
||||
#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
|
||||
#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
|
||||
#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
|
||||
#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
|
||||
|
||||
/* PBA ECC Register */
|
||||
#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
|
||||
#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
|
||||
#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */
|
||||
#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
|
||||
#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
|
||||
|
||||
/*
|
||||
* This defines the bits that are set in the Interrupt Mask
|
||||
* Set/Read Register. Each bit is documented below:
|
||||
* o RXT0 = Receiver Timer Interrupt (ring 0)
|
||||
* o TXDW = Transmit Descriptor Written Back
|
||||
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
|
||||
* o RXSEQ = Receive Sequence Error
|
||||
* o LSC = Link Status Change
|
||||
*/
|
||||
#define IMS_ENABLE_MASK ( \
|
||||
E1000_IMS_RXT0 | \
|
||||
E1000_IMS_TXDW | \
|
||||
E1000_IMS_RXDMT0 | \
|
||||
E1000_IMS_RXSEQ | \
|
||||
E1000_IMS_LSC)
|
||||
|
||||
/* Interrupt Mask Set */
|
||||
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
|
||||
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
|
||||
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
|
||||
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
|
||||
#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
|
||||
#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
|
||||
#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
|
||||
#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
|
||||
#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
|
||||
|
||||
/* Interrupt Cause Set */
|
||||
#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
|
||||
#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
|
||||
#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
|
||||
|
||||
/* Transmit Descriptor Control */
|
||||
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
|
||||
#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
|
||||
#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
|
||||
#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
|
||||
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
|
||||
#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
|
||||
/* Enable the counting of desc. still to be processed. */
|
||||
#define E1000_TXDCTL_COUNT_DESC 0x00400000
|
||||
|
||||
/* Flow Control Constants */
|
||||
#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
|
||||
#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
|
||||
#define FLOW_CONTROL_TYPE 0x8808
|
||||
|
||||
/* 802.1q VLAN Packet Size */
|
||||
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
|
||||
|
||||
/* Receive Address */
|
||||
/*
|
||||
* Number of high/low register pairs in the RAR. The RAR (Receive Address
|
||||
* Registers) holds the directed and multicast addresses that we monitor.
|
||||
* Technically, we have 16 spots. However, we reserve one of these spots
|
||||
* (RAR[15]) for our directed address used by controllers with
|
||||
* manageability enabled, allowing us room for 15 multicast addresses.
|
||||
*/
|
||||
#define E1000_RAR_ENTRIES 15
|
||||
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
|
||||
#define E1000_RAL_MAC_ADDR_LEN 4
|
||||
#define E1000_RAH_MAC_ADDR_LEN 2
|
||||
|
||||
/* Error Codes */
|
||||
#define E1000_ERR_NVM 1
|
||||
#define E1000_ERR_PHY 2
|
||||
#define E1000_ERR_CONFIG 3
|
||||
#define E1000_ERR_PARAM 4
|
||||
#define E1000_ERR_MAC_INIT 5
|
||||
#define E1000_ERR_PHY_TYPE 6
|
||||
#define E1000_ERR_RESET 9
|
||||
#define E1000_ERR_MASTER_REQUESTS_PENDING 10
|
||||
#define E1000_ERR_HOST_INTERFACE_COMMAND 11
|
||||
#define E1000_BLK_PHY_RESET 12
|
||||
#define E1000_ERR_SWFW_SYNC 13
|
||||
#define E1000_NOT_IMPLEMENTED 14
|
||||
#define E1000_ERR_INVALID_ARGUMENT 16
|
||||
#define E1000_ERR_NO_SPACE 17
|
||||
#define E1000_ERR_NVM_PBA_SECTION 18
|
||||
|
||||
/* Loop limit on how long we wait for auto-negotiation to complete */
|
||||
#define FIBER_LINK_UP_LIMIT 50
|
||||
#define COPPER_LINK_UP_LIMIT 10
|
||||
#define PHY_AUTO_NEG_LIMIT 45
|
||||
#define PHY_FORCE_LIMIT 20
|
||||
/* Number of 100 microseconds we wait for PCI Express master disable */
|
||||
#define MASTER_DISABLE_TIMEOUT 800
|
||||
/* Number of milliseconds we wait for PHY configuration done after MAC reset */
|
||||
#define PHY_CFG_TIMEOUT 100
|
||||
/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
|
||||
#define MDIO_OWNERSHIP_TIMEOUT 10
|
||||
/* Number of milliseconds for NVM auto read done after MAC reset. */
|
||||
#define AUTO_READ_DONE_TIMEOUT 10
|
||||
|
||||
/* Flow Control */
|
||||
#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
|
||||
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
|
||||
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
|
||||
|
||||
/* Transmit Configuration Word */
|
||||
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
|
||||
#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
|
||||
#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
|
||||
#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
|
||||
#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
|
||||
|
||||
/* Receive Configuration Word */
|
||||
#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
|
||||
#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
|
||||
#define E1000_RXCW_C 0x20000000 /* Receive config */
|
||||
#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
|
||||
|
||||
/* PCI Express Control */
|
||||
#define E1000_GCR_RXD_NO_SNOOP 0x00000001
|
||||
#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
|
||||
#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
|
||||
#define E1000_GCR_TXD_NO_SNOOP 0x00000008
|
||||
#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
|
||||
#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
|
||||
|
||||
#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
|
||||
E1000_GCR_RXDSCW_NO_SNOOP | \
|
||||
E1000_GCR_RXDSCR_NO_SNOOP | \
|
||||
E1000_GCR_TXD_NO_SNOOP | \
|
||||
E1000_GCR_TXDSCW_NO_SNOOP | \
|
||||
E1000_GCR_TXDSCR_NO_SNOOP)
|
||||
|
||||
/* PHY Control Register */
|
||||
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
|
||||
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
|
||||
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
|
||||
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
|
||||
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
#define MII_CR_SPEED_1000 0x0040
|
||||
#define MII_CR_SPEED_100 0x2000
|
||||
#define MII_CR_SPEED_10 0x0000
|
||||
|
||||
/* PHY Status Register */
|
||||
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
|
||||
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
|
||||
|
||||
/* Autoneg Advertisement Register */
|
||||
#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
|
||||
#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
|
||||
#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
|
||||
#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
|
||||
#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
|
||||
#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
|
||||
|
||||
/* Link Partner Ability Register (Base Page) */
|
||||
#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
|
||||
#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
|
||||
|
||||
/* Autoneg Expansion Register */
|
||||
#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
|
||||
|
||||
/* 1000BASE-T Control Register */
|
||||
#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
|
||||
#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
|
||||
/* 0=DTE device */
|
||||
#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
|
||||
/* 0=Configure PHY as Slave */
|
||||
#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
|
||||
/* 0=Automatic Master/Slave config */
|
||||
|
||||
/* 1000BASE-T Status Register */
|
||||
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
|
||||
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
|
||||
|
||||
|
||||
/* PHY 1000 MII Register/Bit Definitions */
|
||||
/* PHY Registers defined by IEEE */
|
||||
#define PHY_CONTROL 0x00 /* Control Register */
|
||||
#define PHY_STATUS 0x01 /* Status Register */
|
||||
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
|
||||
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
|
||||
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
|
||||
#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
|
||||
#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
|
||||
#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
|
||||
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
|
||||
#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
|
||||
|
||||
#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
|
||||
|
||||
/* NVM Control */
|
||||
#define E1000_EECD_SK 0x00000001 /* NVM Clock */
|
||||
#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
|
||||
#define E1000_EECD_DI 0x00000004 /* NVM Data In */
|
||||
#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
|
||||
#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
|
||||
#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
|
||||
#define E1000_EECD_PRES 0x00000100 /* NVM Present */
|
||||
#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
|
||||
/* NVM Addressing bits based on type (0-small, 1-large) */
|
||||
#define E1000_EECD_ADDR_BITS 0x00000400
|
||||
#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
|
||||
#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
|
||||
#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
|
||||
#define E1000_EECD_SIZE_EX_SHIFT 11
|
||||
#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
|
||||
#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
|
||||
#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
|
||||
#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
|
||||
|
||||
#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
|
||||
#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
|
||||
#define E1000_NVM_RW_REG_START 1 /* Start operation */
|
||||
#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
|
||||
#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
|
||||
#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
|
||||
#define E1000_FLASH_UPDATES 2000
|
||||
|
||||
/* NVM Word Offsets */
|
||||
#define NVM_COMPAT 0x0003
|
||||
#define NVM_ID_LED_SETTINGS 0x0004
|
||||
#define NVM_INIT_CONTROL2_REG 0x000F
|
||||
#define NVM_INIT_CONTROL3_PORT_B 0x0014
|
||||
#define NVM_INIT_3GIO_3 0x001A
|
||||
#define NVM_INIT_CONTROL3_PORT_A 0x0024
|
||||
#define NVM_CFG 0x0012
|
||||
#define NVM_ALT_MAC_ADDR_PTR 0x0037
|
||||
#define NVM_CHECKSUM_REG 0x003F
|
||||
|
||||
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
|
||||
|
||||
#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
|
||||
#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
|
||||
|
||||
/* Mask bits for fields in Word 0x0f of the NVM */
|
||||
#define NVM_WORD0F_PAUSE_MASK 0x3000
|
||||
#define NVM_WORD0F_PAUSE 0x1000
|
||||
#define NVM_WORD0F_ASM_DIR 0x2000
|
||||
|
||||
/* Mask bits for fields in Word 0x1a of the NVM */
|
||||
#define NVM_WORD1A_ASPM_MASK 0x000C
|
||||
|
||||
/* Mask bits for fields in Word 0x03 of the EEPROM */
|
||||
#define NVM_COMPAT_LOM 0x0800
|
||||
|
||||
/* length of string needed to store PBA number */
|
||||
#define E1000_PBANUM_LENGTH 11
|
||||
|
||||
/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
|
||||
#define NVM_SUM 0xBABA
|
||||
|
||||
/* PBA (printed board assembly) number words */
|
||||
#define NVM_PBA_OFFSET_0 8
|
||||
#define NVM_PBA_OFFSET_1 9
|
||||
#define NVM_PBA_PTR_GUARD 0xFAFA
|
||||
#define NVM_WORD_SIZE_BASE_SHIFT 6
|
||||
|
||||
/* NVM Commands - SPI */
|
||||
#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
|
||||
#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
|
||||
#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
|
||||
#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
|
||||
#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
|
||||
#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
|
||||
|
||||
/* SPI NVM Status Register */
|
||||
#define NVM_STATUS_RDY_SPI 0x01
|
||||
|
||||
/* Word definitions for ID LED Settings */
|
||||
#define ID_LED_RESERVED_0000 0x0000
|
||||
#define ID_LED_RESERVED_FFFF 0xFFFF
|
||||
#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
|
||||
(ID_LED_OFF1_OFF2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
#define ID_LED_DEF1_DEF2 0x1
|
||||
#define ID_LED_DEF1_ON2 0x2
|
||||
#define ID_LED_DEF1_OFF2 0x3
|
||||
#define ID_LED_ON1_DEF2 0x4
|
||||
#define ID_LED_ON1_ON2 0x5
|
||||
#define ID_LED_ON1_OFF2 0x6
|
||||
#define ID_LED_OFF1_DEF2 0x7
|
||||
#define ID_LED_OFF1_ON2 0x8
|
||||
#define ID_LED_OFF1_OFF2 0x9
|
||||
|
||||
#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
|
||||
#define IGP_ACTIVITY_LED_ENABLE 0x0300
|
||||
#define IGP_LED3_MODE 0x07000000
|
||||
|
||||
/* PCI/PCI-X/PCI-EX Config space */
|
||||
#define PCI_HEADER_TYPE_REGISTER 0x0E
|
||||
#define PCIE_LINK_STATUS 0x12
|
||||
|
||||
#define PCI_HEADER_TYPE_MULTIFUNC 0x80
|
||||
#define PCIE_LINK_WIDTH_MASK 0x3F0
|
||||
#define PCIE_LINK_WIDTH_SHIFT 4
|
||||
|
||||
#define PHY_REVISION_MASK 0xFFFFFFF0
|
||||
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
|
||||
#define MAX_PHY_MULTI_PAGE_REG 0xF
|
||||
|
||||
/* Bit definitions for valid PHY IDs. */
|
||||
/*
|
||||
* I = Integrated
|
||||
* E = External
|
||||
*/
|
||||
#define M88E1000_E_PHY_ID 0x01410C50
|
||||
#define M88E1000_I_PHY_ID 0x01410C30
|
||||
#define M88E1011_I_PHY_ID 0x01410C20
|
||||
#define IGP01E1000_I_PHY_ID 0x02A80380
|
||||
#define M88E1111_I_PHY_ID 0x01410CC0
|
||||
#define GG82563_E_PHY_ID 0x01410CA0
|
||||
#define IGP03E1000_E_PHY_ID 0x02A80390
|
||||
#define IFE_E_PHY_ID 0x02A80330
|
||||
#define IFE_PLUS_E_PHY_ID 0x02A80320
|
||||
#define IFE_C_E_PHY_ID 0x02A80310
|
||||
#define BME1000_E_PHY_ID 0x01410CB0
|
||||
#define BME1000_E_PHY_ID_R2 0x01410CB1
|
||||
#define I82577_E_PHY_ID 0x01540050
|
||||
#define I82578_E_PHY_ID 0x004DD040
|
||||
#define I82579_E_PHY_ID 0x01540090
|
||||
|
||||
/* M88E1000 Specific Registers */
|
||||
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
|
||||
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
|
||||
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
|
||||
|
||||
#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
|
||||
#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
|
||||
|
||||
/* M88E1000 PHY Specific Control Register */
|
||||
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
|
||||
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
|
||||
/* Manual MDI configuration */
|
||||
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
|
||||
/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
|
||||
#define M88E1000_PSCR_AUTO_X_1000T 0x0040
|
||||
/* Auto crossover enabled all speeds */
|
||||
#define M88E1000_PSCR_AUTO_X_MODE 0x0060
|
||||
/*
|
||||
* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
|
||||
* 0=Normal 10BASE-T Rx Threshold
|
||||
*/
|
||||
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
|
||||
|
||||
/* M88E1000 PHY Specific Status Register */
|
||||
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
|
||||
#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
|
||||
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
|
||||
/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
|
||||
#define M88E1000_PSSR_CABLE_LENGTH 0x0380
|
||||
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
|
||||
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
|
||||
|
||||
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
|
||||
|
||||
/*
|
||||
* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
* are the master
|
||||
*/
|
||||
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
|
||||
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
|
||||
/*
|
||||
* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
* are the slave
|
||||
*/
|
||||
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
|
||||
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
|
||||
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
|
||||
|
||||
/* M88EC018 Rev 2 specific DownShift settings */
|
||||
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
|
||||
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
|
||||
|
||||
#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
|
||||
#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
|
||||
|
||||
/* BME1000 PHY Specific Control Register */
|
||||
#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
|
||||
|
||||
|
||||
#define PHY_PAGE_SHIFT 5
|
||||
#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
|
||||
((reg) & MAX_PHY_REG_ADDRESS))
|
||||
|
||||
/*
|
||||
* Bits...
|
||||
* 15-5: page
|
||||
* 4-0: register offset
|
||||
*/
|
||||
#define GG82563_PAGE_SHIFT 5
|
||||
#define GG82563_REG(page, reg) \
|
||||
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
|
||||
#define GG82563_MIN_ALT_REG 30
|
||||
|
||||
/* GG82563 Specific Registers */
|
||||
#define GG82563_PHY_SPEC_CTRL \
|
||||
GG82563_REG(0, 16) /* PHY Specific Control */
|
||||
#define GG82563_PHY_PAGE_SELECT \
|
||||
GG82563_REG(0, 22) /* Page Select */
|
||||
#define GG82563_PHY_SPEC_CTRL_2 \
|
||||
GG82563_REG(0, 26) /* PHY Specific Control 2 */
|
||||
#define GG82563_PHY_PAGE_SELECT_ALT \
|
||||
GG82563_REG(0, 29) /* Alternate Page Select */
|
||||
|
||||
#define GG82563_PHY_MAC_SPEC_CTRL \
|
||||
GG82563_REG(2, 21) /* MAC Specific Control Register */
|
||||
|
||||
#define GG82563_PHY_DSP_DISTANCE \
|
||||
GG82563_REG(5, 26) /* DSP Distance */
|
||||
|
||||
/* Page 193 - Port Control Registers */
|
||||
#define GG82563_PHY_KMRN_MODE_CTRL \
|
||||
GG82563_REG(193, 16) /* Kumeran Mode Control */
|
||||
#define GG82563_PHY_PWR_MGMT_CTRL \
|
||||
GG82563_REG(193, 20) /* Power Management Control */
|
||||
|
||||
/* Page 194 - KMRN Registers */
|
||||
#define GG82563_PHY_INBAND_CTRL \
|
||||
GG82563_REG(194, 18) /* Inband Control */
|
||||
|
||||
/* MDI Control */
|
||||
#define E1000_MDIC_REG_SHIFT 16
|
||||
#define E1000_MDIC_PHY_SHIFT 21
|
||||
#define E1000_MDIC_OP_WRITE 0x04000000
|
||||
#define E1000_MDIC_OP_READ 0x08000000
|
||||
#define E1000_MDIC_READY 0x10000000
|
||||
#define E1000_MDIC_ERROR 0x40000000
|
||||
|
||||
/* SerDes Control */
|
||||
#define E1000_GEN_POLL_TIMEOUT 640
|
||||
|
||||
#endif /* _E1000_DEFINES_H_ */
|
||||
736
drivers/net/ethernet/intel/e1000e/e1000.h
Normal file
736
drivers/net/ethernet/intel/e1000e/e1000.h
Normal file
@@ -0,0 +1,736 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2011 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
/* Linux PRO/1000 Ethernet Driver main header file */
|
||||
|
||||
#ifndef _E1000_H_
|
||||
#define _E1000_H_
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-aspm.h>
|
||||
#include <linux/crc32.h>
|
||||
#include <linux/if_vlan.h>
|
||||
|
||||
#include "hw.h"
|
||||
|
||||
struct e1000_info;
|
||||
|
||||
#define e_dbg(format, arg...) \
|
||||
netdev_dbg(hw->adapter->netdev, format, ## arg)
|
||||
#define e_err(format, arg...) \
|
||||
netdev_err(adapter->netdev, format, ## arg)
|
||||
#define e_info(format, arg...) \
|
||||
netdev_info(adapter->netdev, format, ## arg)
|
||||
#define e_warn(format, arg...) \
|
||||
netdev_warn(adapter->netdev, format, ## arg)
|
||||
#define e_notice(format, arg...) \
|
||||
netdev_notice(adapter->netdev, format, ## arg)
|
||||
|
||||
|
||||
/* Interrupt modes, as used by the IntMode parameter */
|
||||
#define E1000E_INT_MODE_LEGACY 0
|
||||
#define E1000E_INT_MODE_MSI 1
|
||||
#define E1000E_INT_MODE_MSIX 2
|
||||
|
||||
/* Tx/Rx descriptor defines */
|
||||
#define E1000_DEFAULT_TXD 256
|
||||
#define E1000_MAX_TXD 4096
|
||||
#define E1000_MIN_TXD 64
|
||||
|
||||
#define E1000_DEFAULT_RXD 256
|
||||
#define E1000_MAX_RXD 4096
|
||||
#define E1000_MIN_RXD 64
|
||||
|
||||
#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
|
||||
#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
|
||||
|
||||
/* Early Receive defines */
|
||||
#define E1000_ERT_2048 0x100
|
||||
|
||||
#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
|
||||
|
||||
/* How many Tx Descriptors do we need to call netif_wake_queue ? */
|
||||
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
||||
#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
|
||||
#define AUTO_ALL_MODES 0
|
||||
#define E1000_EEPROM_APME 0x0400
|
||||
|
||||
#define E1000_MNG_VLAN_NONE (-1)
|
||||
|
||||
/* Number of packet split data buffers (not including the header buffer) */
|
||||
#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
|
||||
|
||||
#define DEFAULT_JUMBO 9234
|
||||
|
||||
/* BM/HV Specific Registers */
|
||||
#define BM_PORT_CTRL_PAGE 769
|
||||
|
||||
#define PHY_UPPER_SHIFT 21
|
||||
#define BM_PHY_REG(page, reg) \
|
||||
(((reg) & MAX_PHY_REG_ADDRESS) |\
|
||||
(((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
|
||||
(((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
|
||||
|
||||
/* PHY Wakeup Registers and defines */
|
||||
#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
|
||||
#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
|
||||
#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
|
||||
#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
|
||||
#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
|
||||
#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
|
||||
#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
|
||||
#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
|
||||
#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
|
||||
#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
|
||||
|
||||
#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
|
||||
#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
|
||||
#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
|
||||
#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
|
||||
#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
|
||||
#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
|
||||
#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
|
||||
|
||||
#define HV_STATS_PAGE 778
|
||||
#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
|
||||
#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
|
||||
#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
|
||||
#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
|
||||
#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
|
||||
#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
|
||||
#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
|
||||
#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
|
||||
#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
|
||||
#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
|
||||
#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
|
||||
#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
|
||||
#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
|
||||
#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
|
||||
|
||||
#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
|
||||
|
||||
/* BM PHY Copper Specific Status */
|
||||
#define BM_CS_STATUS 17
|
||||
#define BM_CS_STATUS_LINK_UP 0x0400
|
||||
#define BM_CS_STATUS_RESOLVED 0x0800
|
||||
#define BM_CS_STATUS_SPEED_MASK 0xC000
|
||||
#define BM_CS_STATUS_SPEED_1000 0x8000
|
||||
|
||||
/* 82577 Mobile Phy Status Register */
|
||||
#define HV_M_STATUS 26
|
||||
#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
|
||||
#define HV_M_STATUS_SPEED_MASK 0x0300
|
||||
#define HV_M_STATUS_SPEED_1000 0x0200
|
||||
#define HV_M_STATUS_LINK_UP 0x0040
|
||||
|
||||
/* Time to wait before putting the device into D3 if there's no link (in ms). */
|
||||
#define LINK_TIMEOUT 100
|
||||
|
||||
#define DEFAULT_RDTR 0
|
||||
#define DEFAULT_RADV 8
|
||||
#define BURST_RDTR 0x20
|
||||
#define BURST_RADV 0x20
|
||||
|
||||
/*
|
||||
* in the case of WTHRESH, it appears at least the 82571/2 hardware
|
||||
* writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
|
||||
* WTHRESH=4, and since we want 64 bytes at a time written back, set
|
||||
* it to 5
|
||||
*/
|
||||
#define E1000_TXDCTL_DMA_BURST_ENABLE \
|
||||
(E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
|
||||
E1000_TXDCTL_COUNT_DESC | \
|
||||
(5 << 16) | /* wthresh must be +1 more than desired */\
|
||||
(1 << 8) | /* hthresh */ \
|
||||
0x1f) /* pthresh */
|
||||
|
||||
#define E1000_RXDCTL_DMA_BURST_ENABLE \
|
||||
(0x01000000 | /* set descriptor granularity */ \
|
||||
(4 << 16) | /* set writeback threshold */ \
|
||||
(4 << 8) | /* set prefetch threshold */ \
|
||||
0x20) /* set hthresh */
|
||||
|
||||
#define E1000_TIDV_FPD (1 << 31)
|
||||
#define E1000_RDTR_FPD (1 << 31)
|
||||
|
||||
enum e1000_boards {
|
||||
board_82571,
|
||||
board_82572,
|
||||
board_82573,
|
||||
board_82574,
|
||||
board_82583,
|
||||
board_80003es2lan,
|
||||
board_ich8lan,
|
||||
board_ich9lan,
|
||||
board_ich10lan,
|
||||
board_pchlan,
|
||||
board_pch2lan,
|
||||
};
|
||||
|
||||
struct e1000_ps_page {
|
||||
struct page *page;
|
||||
u64 dma; /* must be u64 - written to hw */
|
||||
};
|
||||
|
||||
/*
|
||||
* wrappers around a pointer to a socket buffer,
|
||||
* so a DMA handle can be stored along with the buffer
|
||||
*/
|
||||
struct e1000_buffer {
|
||||
dma_addr_t dma;
|
||||
struct sk_buff *skb;
|
||||
union {
|
||||
/* Tx */
|
||||
struct {
|
||||
unsigned long time_stamp;
|
||||
u16 length;
|
||||
u16 next_to_watch;
|
||||
unsigned int segs;
|
||||
unsigned int bytecount;
|
||||
u16 mapped_as_page;
|
||||
};
|
||||
/* Rx */
|
||||
struct {
|
||||
/* arrays of page information for packet split */
|
||||
struct e1000_ps_page *ps_pages;
|
||||
struct page *page;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct e1000_ring {
|
||||
void *desc; /* pointer to ring memory */
|
||||
dma_addr_t dma; /* phys address of ring */
|
||||
unsigned int size; /* length of ring in bytes */
|
||||
unsigned int count; /* number of desc. in ring */
|
||||
|
||||
u16 next_to_use;
|
||||
u16 next_to_clean;
|
||||
|
||||
u16 head;
|
||||
u16 tail;
|
||||
|
||||
/* array of buffer information structs */
|
||||
struct e1000_buffer *buffer_info;
|
||||
|
||||
char name[IFNAMSIZ + 5];
|
||||
u32 ims_val;
|
||||
u32 itr_val;
|
||||
u16 itr_register;
|
||||
int set_itr;
|
||||
|
||||
struct sk_buff *rx_skb_top;
|
||||
};
|
||||
|
||||
/* PHY register snapshot values */
|
||||
struct e1000_phy_regs {
|
||||
u16 bmcr; /* basic mode control register */
|
||||
u16 bmsr; /* basic mode status register */
|
||||
u16 advertise; /* auto-negotiation advertisement */
|
||||
u16 lpa; /* link partner ability register */
|
||||
u16 expansion; /* auto-negotiation expansion reg */
|
||||
u16 ctrl1000; /* 1000BASE-T control register */
|
||||
u16 stat1000; /* 1000BASE-T status register */
|
||||
u16 estatus; /* extended status register */
|
||||
};
|
||||
|
||||
/* board specific private data structure */
|
||||
struct e1000_adapter {
|
||||
struct timer_list watchdog_timer;
|
||||
struct timer_list phy_info_timer;
|
||||
struct timer_list blink_timer;
|
||||
|
||||
struct work_struct reset_task;
|
||||
struct work_struct watchdog_task;
|
||||
|
||||
const struct e1000_info *ei;
|
||||
|
||||
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
||||
u32 bd_number;
|
||||
u32 rx_buffer_len;
|
||||
u16 mng_vlan_id;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
u16 eeprom_vers;
|
||||
|
||||
/* track device up/down/testing state */
|
||||
unsigned long state;
|
||||
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 itr;
|
||||
u32 itr_setting;
|
||||
u16 tx_itr;
|
||||
u16 rx_itr;
|
||||
|
||||
/*
|
||||
* Tx
|
||||
*/
|
||||
struct e1000_ring *tx_ring /* One per active queue */
|
||||
____cacheline_aligned_in_smp;
|
||||
|
||||
struct napi_struct napi;
|
||||
|
||||
unsigned int restart_queue;
|
||||
u32 txd_cmd;
|
||||
|
||||
bool detect_tx_hung;
|
||||
u8 tx_timeout_factor;
|
||||
|
||||
u32 tx_int_delay;
|
||||
u32 tx_abs_int_delay;
|
||||
|
||||
unsigned int total_tx_bytes;
|
||||
unsigned int total_tx_packets;
|
||||
unsigned int total_rx_bytes;
|
||||
unsigned int total_rx_packets;
|
||||
|
||||
/* Tx stats */
|
||||
u64 tpt_old;
|
||||
u64 colc_old;
|
||||
u32 gotc;
|
||||
u64 gotc_old;
|
||||
u32 tx_timeout_count;
|
||||
u32 tx_fifo_head;
|
||||
u32 tx_head_addr;
|
||||
u32 tx_fifo_size;
|
||||
u32 tx_dma_failed;
|
||||
|
||||
/*
|
||||
* Rx
|
||||
*/
|
||||
bool (*clean_rx) (struct e1000_adapter *adapter,
|
||||
int *work_done, int work_to_do)
|
||||
____cacheline_aligned_in_smp;
|
||||
void (*alloc_rx_buf) (struct e1000_adapter *adapter,
|
||||
int cleaned_count, gfp_t gfp);
|
||||
struct e1000_ring *rx_ring;
|
||||
|
||||
u32 rx_int_delay;
|
||||
u32 rx_abs_int_delay;
|
||||
|
||||
/* Rx stats */
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
u64 rx_hdr_split;
|
||||
u32 gorc;
|
||||
u64 gorc_old;
|
||||
u32 alloc_rx_buff_failed;
|
||||
u32 rx_dma_failed;
|
||||
|
||||
unsigned int rx_ps_pages;
|
||||
u16 rx_ps_bsize0;
|
||||
u32 max_frame_size;
|
||||
u32 min_frame_size;
|
||||
|
||||
/* OS defined structs */
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
/* structs defined in e1000_hw.h */
|
||||
struct e1000_hw hw;
|
||||
|
||||
spinlock_t stats64_lock;
|
||||
struct e1000_hw_stats stats;
|
||||
struct e1000_phy_info phy_info;
|
||||
struct e1000_phy_stats phy_stats;
|
||||
|
||||
/* Snapshot of PHY registers */
|
||||
struct e1000_phy_regs phy_regs;
|
||||
|
||||
struct e1000_ring test_tx_ring;
|
||||
struct e1000_ring test_rx_ring;
|
||||
u32 test_icr;
|
||||
|
||||
u32 msg_enable;
|
||||
unsigned int num_vectors;
|
||||
struct msix_entry *msix_entries;
|
||||
int int_mode;
|
||||
u32 eiac_mask;
|
||||
|
||||
u32 eeprom_wol;
|
||||
u32 wol;
|
||||
u32 pba;
|
||||
u32 max_hw_frame_size;
|
||||
|
||||
bool fc_autoneg;
|
||||
|
||||
unsigned int flags;
|
||||
unsigned int flags2;
|
||||
struct work_struct downshift_task;
|
||||
struct work_struct update_phy_task;
|
||||
struct work_struct print_hang_task;
|
||||
|
||||
bool idle_check;
|
||||
int phy_hang_count;
|
||||
};
|
||||
|
||||
struct e1000_info {
|
||||
enum e1000_mac_type mac;
|
||||
unsigned int flags;
|
||||
unsigned int flags2;
|
||||
u32 pba;
|
||||
u32 max_hw_frame_size;
|
||||
s32 (*get_variants)(struct e1000_adapter *);
|
||||
struct e1000_mac_operations *mac_ops;
|
||||
struct e1000_phy_operations *phy_ops;
|
||||
struct e1000_nvm_operations *nvm_ops;
|
||||
};
|
||||
|
||||
/* hardware capability, feature, and workaround flags */
|
||||
#define FLAG_HAS_AMT (1 << 0)
|
||||
#define FLAG_HAS_FLASH (1 << 1)
|
||||
#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
|
||||
#define FLAG_HAS_WOL (1 << 3)
|
||||
#define FLAG_HAS_ERT (1 << 4)
|
||||
#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
|
||||
#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
|
||||
#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
|
||||
#define FLAG_READ_ONLY_NVM (1 << 8)
|
||||
#define FLAG_IS_ICH (1 << 9)
|
||||
#define FLAG_HAS_MSIX (1 << 10)
|
||||
#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
|
||||
#define FLAG_IS_QUAD_PORT_A (1 << 12)
|
||||
#define FLAG_IS_QUAD_PORT (1 << 13)
|
||||
#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
|
||||
#define FLAG_APME_IN_WUC (1 << 15)
|
||||
#define FLAG_APME_IN_CTRL3 (1 << 16)
|
||||
#define FLAG_APME_CHECK_PORT_B (1 << 17)
|
||||
#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
|
||||
#define FLAG_NO_WAKE_UCAST (1 << 19)
|
||||
#define FLAG_MNG_PT_ENABLED (1 << 20)
|
||||
#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
|
||||
#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
|
||||
#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
|
||||
#define FLAG_RX_NEEDS_RESTART (1 << 24)
|
||||
#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
|
||||
#define FLAG_SMART_POWER_DOWN (1 << 26)
|
||||
#define FLAG_MSI_ENABLED (1 << 27)
|
||||
#define FLAG_RX_CSUM_ENABLED (1 << 28)
|
||||
#define FLAG_TSO_FORCE (1 << 29)
|
||||
#define FLAG_RX_RESTART_NOW (1 << 30)
|
||||
#define FLAG_MSI_TEST_FAILED (1 << 31)
|
||||
|
||||
/* CRC Stripping defines */
|
||||
#define FLAG2_CRC_STRIPPING (1 << 0)
|
||||
#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
|
||||
#define FLAG2_IS_DISCARDING (1 << 2)
|
||||
#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
|
||||
#define FLAG2_HAS_PHY_STATS (1 << 4)
|
||||
#define FLAG2_HAS_EEE (1 << 5)
|
||||
#define FLAG2_DMA_BURST (1 << 6)
|
||||
#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
|
||||
#define FLAG2_DISABLE_AIM (1 << 8)
|
||||
#define FLAG2_CHECK_PHY_HANG (1 << 9)
|
||||
|
||||
#define E1000_RX_DESC_PS(R, i) \
|
||||
(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
|
||||
#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
|
||||
#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
|
||||
#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
|
||||
#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
|
||||
|
||||
enum e1000_state_t {
|
||||
__E1000_TESTING,
|
||||
__E1000_RESETTING,
|
||||
__E1000_DOWN
|
||||
};
|
||||
|
||||
enum latency_range {
|
||||
lowest_latency = 0,
|
||||
low_latency = 1,
|
||||
bulk_latency = 2,
|
||||
latency_invalid = 255
|
||||
};
|
||||
|
||||
extern char e1000e_driver_name[];
|
||||
extern const char e1000e_driver_version[];
|
||||
|
||||
extern void e1000e_check_options(struct e1000_adapter *adapter);
|
||||
extern void e1000e_set_ethtool_ops(struct net_device *netdev);
|
||||
|
||||
extern int e1000e_up(struct e1000_adapter *adapter);
|
||||
extern void e1000e_down(struct e1000_adapter *adapter);
|
||||
extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
|
||||
extern void e1000e_reset(struct e1000_adapter *adapter);
|
||||
extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
|
||||
extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
|
||||
extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
|
||||
extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
|
||||
extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
|
||||
extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
|
||||
struct rtnl_link_stats64
|
||||
*stats);
|
||||
extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
|
||||
extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
|
||||
extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
|
||||
extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
|
||||
|
||||
extern unsigned int copybreak;
|
||||
|
||||
extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
|
||||
|
||||
extern struct e1000_info e1000_82571_info;
|
||||
extern struct e1000_info e1000_82572_info;
|
||||
extern struct e1000_info e1000_82573_info;
|
||||
extern struct e1000_info e1000_82574_info;
|
||||
extern struct e1000_info e1000_82583_info;
|
||||
extern struct e1000_info e1000_ich8_info;
|
||||
extern struct e1000_info e1000_ich9_info;
|
||||
extern struct e1000_info e1000_ich10_info;
|
||||
extern struct e1000_info e1000_pch_info;
|
||||
extern struct e1000_info e1000_pch2_info;
|
||||
extern struct e1000_info e1000_es2_info;
|
||||
|
||||
extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
|
||||
u32 pba_num_size);
|
||||
|
||||
extern s32 e1000e_commit_phy(struct e1000_hw *hw);
|
||||
|
||||
extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
|
||||
|
||||
extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
|
||||
extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
|
||||
|
||||
extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
|
||||
extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
|
||||
bool state);
|
||||
extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
|
||||
extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
|
||||
extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
|
||||
extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
|
||||
extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
|
||||
extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
|
||||
extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
|
||||
|
||||
extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
|
||||
extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
|
||||
extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
|
||||
extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
|
||||
extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
|
||||
extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
|
||||
extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
|
||||
extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
|
||||
extern s32 e1000e_id_led_init(struct e1000_hw *hw);
|
||||
extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
|
||||
extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
|
||||
extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
|
||||
extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
|
||||
extern s32 e1000e_setup_link(struct e1000_hw *hw);
|
||||
extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
|
||||
extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
|
||||
extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list,
|
||||
u32 mc_addr_count);
|
||||
extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
|
||||
extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
|
||||
extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
|
||||
extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
|
||||
extern void e1000e_config_collision_dist(struct e1000_hw *hw);
|
||||
extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
|
||||
extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
|
||||
extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
|
||||
extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
|
||||
extern void e1000e_reset_adaptive(struct e1000_hw *hw);
|
||||
extern void e1000e_update_adaptive(struct e1000_hw *hw);
|
||||
|
||||
extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
|
||||
extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
|
||||
extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
|
||||
extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
|
||||
extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
|
||||
u16 *data);
|
||||
extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
|
||||
extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
|
||||
u16 data);
|
||||
extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
|
||||
extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
|
||||
extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
|
||||
extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
|
||||
extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
|
||||
extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
|
||||
extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
|
||||
u16 *phy_reg);
|
||||
extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
|
||||
u16 *phy_reg);
|
||||
extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
|
||||
extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
|
||||
u16 data);
|
||||
extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
|
||||
u16 *data);
|
||||
extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
|
||||
u32 usec_interval, bool *success);
|
||||
extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
|
||||
extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
|
||||
extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
|
||||
extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern s32 e1000e_check_downshift(struct e1000_hw *hw);
|
||||
extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
|
||||
u16 *data);
|
||||
extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
|
||||
u16 *data);
|
||||
extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
|
||||
u16 data);
|
||||
extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
|
||||
u16 data);
|
||||
extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
|
||||
extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
|
||||
extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
|
||||
extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
|
||||
extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
|
||||
extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
|
||||
|
||||
extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
|
||||
extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
|
||||
extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
|
||||
extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
|
||||
extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
|
||||
extern bool e1000_check_phy_82574(struct e1000_hw *hw);
|
||||
|
||||
static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->phy.ops.reset(hw);
|
||||
}
|
||||
|
||||
static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->phy.ops.check_reset_block(hw);
|
||||
}
|
||||
|
||||
static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
|
||||
{
|
||||
return hw->phy.ops.read_reg(hw, offset, data);
|
||||
}
|
||||
|
||||
static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
|
||||
{
|
||||
return hw->phy.ops.write_reg(hw, offset, data);
|
||||
}
|
||||
|
||||
static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->phy.ops.get_cable_length(hw);
|
||||
}
|
||||
|
||||
extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
|
||||
extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
||||
extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
|
||||
extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
|
||||
extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
||||
extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
|
||||
extern void e1000e_release_nvm(struct e1000_hw *hw);
|
||||
extern void e1000e_reload_nvm(struct e1000_hw *hw);
|
||||
extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
|
||||
|
||||
static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
|
||||
{
|
||||
if (hw->mac.ops.read_mac_addr)
|
||||
return hw->mac.ops.read_mac_addr(hw);
|
||||
|
||||
return e1000_read_mac_addr_generic(hw);
|
||||
}
|
||||
|
||||
static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->nvm.ops.validate(hw);
|
||||
}
|
||||
|
||||
static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->nvm.ops.update(hw);
|
||||
}
|
||||
|
||||
static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
||||
{
|
||||
return hw->nvm.ops.read(hw, offset, words, data);
|
||||
}
|
||||
|
||||
static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
||||
{
|
||||
return hw->nvm.ops.write(hw, offset, words, data);
|
||||
}
|
||||
|
||||
static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->phy.ops.get_info(hw);
|
||||
}
|
||||
|
||||
static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
|
||||
{
|
||||
return hw->mac.ops.check_mng_mode(hw);
|
||||
}
|
||||
|
||||
extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
|
||||
extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
|
||||
extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
|
||||
|
||||
static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
|
||||
{
|
||||
return readl(hw->hw_addr + reg);
|
||||
}
|
||||
|
||||
static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
|
||||
{
|
||||
writel(val, hw->hw_addr + reg);
|
||||
}
|
||||
|
||||
#endif /* _E1000_H_ */
|
||||
2081
drivers/net/ethernet/intel/e1000e/ethtool.c
Normal file
2081
drivers/net/ethernet/intel/e1000e/ethtool.c
Normal file
File diff suppressed because it is too large
Load Diff
984
drivers/net/ethernet/intel/e1000e/hw.h
Normal file
984
drivers/net/ethernet/intel/e1000e/hw.h
Normal file
@@ -0,0 +1,984 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2011 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _E1000_HW_H_
|
||||
#define _E1000_HW_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct e1000_hw;
|
||||
struct e1000_adapter;
|
||||
|
||||
#include "defines.h"
|
||||
|
||||
#define er32(reg) __er32(hw, E1000_##reg)
|
||||
#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
|
||||
#define e1e_flush() er32(STATUS)
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
|
||||
(writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY(a, reg, offset) \
|
||||
(readl((a)->hw_addr + reg + ((offset) << 2)))
|
||||
|
||||
enum e1e_registers {
|
||||
E1000_CTRL = 0x00000, /* Device Control - RW */
|
||||
E1000_STATUS = 0x00008, /* Device Status - RO */
|
||||
E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
|
||||
E1000_EERD = 0x00014, /* EEPROM Read - RW */
|
||||
E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
|
||||
E1000_FLA = 0x0001C, /* Flash Access - RW */
|
||||
E1000_MDIC = 0x00020, /* MDI Control - RW */
|
||||
E1000_SCTL = 0x00024, /* SerDes Control - RW */
|
||||
E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
|
||||
E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
|
||||
E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
|
||||
E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
|
||||
E1000_FCT = 0x00030, /* Flow Control Type - RW */
|
||||
E1000_VET = 0x00038, /* VLAN Ether Type - RW */
|
||||
E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
|
||||
E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
|
||||
E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
|
||||
E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
|
||||
E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
|
||||
E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
|
||||
E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
|
||||
E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
|
||||
E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
|
||||
#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
|
||||
E1000_RCTL = 0x00100, /* Rx Control - RW */
|
||||
E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
|
||||
E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
|
||||
E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
|
||||
E1000_TCTL = 0x00400, /* Tx Control - RW */
|
||||
E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
|
||||
E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
|
||||
E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
|
||||
E1000_LEDCTL = 0x00E00, /* LED Control - RW */
|
||||
E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
|
||||
E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
|
||||
E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
|
||||
#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
|
||||
E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
|
||||
E1000_PBS = 0x01008, /* Packet Buffer Size */
|
||||
E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
|
||||
E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
|
||||
E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
|
||||
E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
|
||||
E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
|
||||
E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
|
||||
E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
|
||||
E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
|
||||
E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
|
||||
E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
|
||||
E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
|
||||
E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
|
||||
E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
|
||||
E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
|
||||
E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
|
||||
#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
|
||||
E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
|
||||
|
||||
/* Convenience macros
|
||||
*
|
||||
* Note: "_n" is the queue number of the register to be written to.
|
||||
*
|
||||
* Example usage:
|
||||
* E1000_RDBAL_REG(current_rx_queue)
|
||||
*
|
||||
*/
|
||||
#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
|
||||
E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
|
||||
E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
|
||||
E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
|
||||
E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
|
||||
E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
|
||||
E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
|
||||
E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
|
||||
E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
|
||||
#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
|
||||
E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
|
||||
E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
|
||||
#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
|
||||
E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
|
||||
E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
|
||||
E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
|
||||
E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
|
||||
E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
|
||||
E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
|
||||
E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
|
||||
E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
|
||||
E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
|
||||
E1000_COLC = 0x04028, /* Collision Count - R/clr */
|
||||
E1000_DC = 0x04030, /* Defer Count - R/clr */
|
||||
E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
|
||||
E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
|
||||
E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
|
||||
E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
|
||||
E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
|
||||
E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
|
||||
E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
|
||||
E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
|
||||
E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
|
||||
E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
|
||||
E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
|
||||
E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
|
||||
E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
|
||||
E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
|
||||
E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
|
||||
E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
|
||||
E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
|
||||
E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
|
||||
E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
|
||||
E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
|
||||
E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
|
||||
E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
|
||||
E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
|
||||
E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
|
||||
E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
|
||||
E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
|
||||
E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
|
||||
E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
|
||||
E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
|
||||
E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
|
||||
E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
|
||||
E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
|
||||
E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
|
||||
E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
|
||||
E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
|
||||
E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
|
||||
E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
|
||||
E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
|
||||
E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
|
||||
E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
|
||||
E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
|
||||
E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
|
||||
E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
|
||||
E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
|
||||
E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
|
||||
E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
|
||||
E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
|
||||
E1000_IAC = 0x04100, /* Interrupt Assertion Count */
|
||||
E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
|
||||
E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
|
||||
E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
|
||||
E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
|
||||
E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
|
||||
E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
|
||||
E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
|
||||
E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
|
||||
E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
|
||||
E1000_RFCTL = 0x05008, /* Receive Filter Control */
|
||||
E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
|
||||
E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
|
||||
#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
|
||||
#define E1000_RA (E1000_RAL(0))
|
||||
E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
|
||||
#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
|
||||
E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
|
||||
E1000_WUC = 0x05800, /* Wakeup Control - RW */
|
||||
E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
|
||||
E1000_WUS = 0x05810, /* Wakeup Status - RO */
|
||||
E1000_MANC = 0x05820, /* Management Control - RW */
|
||||
E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
|
||||
E1000_HOST_IF = 0x08800, /* Host Interface */
|
||||
|
||||
E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
|
||||
E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
|
||||
E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
|
||||
#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
|
||||
E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
|
||||
E1000_GCR = 0x05B00, /* PCI-Ex Control */
|
||||
E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
|
||||
E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
|
||||
E1000_SWSM = 0x05B50, /* SW Semaphore */
|
||||
E1000_FWSM = 0x05B54, /* FW Semaphore */
|
||||
E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
|
||||
E1000_FFLT_DBG = 0x05F04, /* Debug Register */
|
||||
E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
|
||||
#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
|
||||
#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
|
||||
E1000_HICR = 0x08F00, /* Host Interface Control */
|
||||
};
|
||||
|
||||
#define E1000_MAX_PHY_ADDR 4
|
||||
|
||||
/* IGP01E1000 Specific Registers */
|
||||
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
|
||||
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
|
||||
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
|
||||
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
|
||||
#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
|
||||
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
|
||||
#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
|
||||
#define IGP_PAGE_SHIFT 5
|
||||
#define PHY_REG_MASK 0x1F
|
||||
|
||||
#define BM_WUC_PAGE 800
|
||||
#define BM_WUC_ADDRESS_OPCODE 0x11
|
||||
#define BM_WUC_DATA_OPCODE 0x12
|
||||
#define BM_WUC_ENABLE_PAGE 769
|
||||
#define BM_WUC_ENABLE_REG 17
|
||||
#define BM_WUC_ENABLE_BIT (1 << 2)
|
||||
#define BM_WUC_HOST_WU_BIT (1 << 4)
|
||||
#define BM_WUC_ME_WU_BIT (1 << 5)
|
||||
|
||||
#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
|
||||
#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
|
||||
#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
|
||||
|
||||
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
|
||||
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
|
||||
|
||||
#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
|
||||
#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
|
||||
|
||||
#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
|
||||
|
||||
#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
|
||||
#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
|
||||
#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
|
||||
|
||||
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
|
||||
|
||||
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
|
||||
#define IGP01E1000_PSSR_MDIX 0x0800
|
||||
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
|
||||
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
|
||||
|
||||
#define IGP02E1000_PHY_CHANNEL_NUM 4
|
||||
#define IGP02E1000_PHY_AGC_A 0x11B1
|
||||
#define IGP02E1000_PHY_AGC_B 0x12B1
|
||||
#define IGP02E1000_PHY_AGC_C 0x14B1
|
||||
#define IGP02E1000_PHY_AGC_D 0x18B1
|
||||
|
||||
#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
|
||||
#define IGP02E1000_AGC_LENGTH_MASK 0x7F
|
||||
#define IGP02E1000_AGC_RANGE 15
|
||||
|
||||
/* manage.c */
|
||||
#define E1000_VFTA_ENTRY_SHIFT 5
|
||||
#define E1000_VFTA_ENTRY_MASK 0x7F
|
||||
#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
|
||||
|
||||
#define E1000_HICR_EN 0x01 /* Enable bit - RO */
|
||||
/* Driver sets this bit when done to put command in RAM */
|
||||
#define E1000_HICR_C 0x02
|
||||
#define E1000_HICR_FW_RESET_ENABLE 0x40
|
||||
#define E1000_HICR_FW_RESET 0x80
|
||||
|
||||
#define E1000_FWSM_MODE_MASK 0xE
|
||||
#define E1000_FWSM_MODE_SHIFT 1
|
||||
|
||||
#define E1000_MNG_IAMT_MODE 0x3
|
||||
#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
|
||||
#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
|
||||
#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
|
||||
#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
|
||||
|
||||
/* nvm.c */
|
||||
#define E1000_STM_OPCODE 0xDB00
|
||||
|
||||
#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
|
||||
#define E1000_KMRNCTRLSTA_REN 0x00200000
|
||||
#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
|
||||
#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
|
||||
#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
|
||||
#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
|
||||
#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
|
||||
#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
|
||||
#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
|
||||
#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
|
||||
#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
|
||||
|
||||
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
|
||||
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
|
||||
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
|
||||
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
|
||||
|
||||
/* IFE PHY Extended Status Control */
|
||||
#define IFE_PESC_POLARITY_REVERSED 0x0100
|
||||
|
||||
/* IFE PHY Special Control */
|
||||
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
|
||||
#define IFE_PSC_FORCE_POLARITY 0x0020
|
||||
|
||||
/* IFE PHY Special Control and LED Control */
|
||||
#define IFE_PSCL_PROBE_MODE 0x0020
|
||||
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
|
||||
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
|
||||
|
||||
/* IFE PHY MDIX Control */
|
||||
#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
|
||||
#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
|
||||
#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
|
||||
|
||||
#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
|
||||
|
||||
#define E1000_DEV_ID_82571EB_COPPER 0x105E
|
||||
#define E1000_DEV_ID_82571EB_FIBER 0x105F
|
||||
#define E1000_DEV_ID_82571EB_SERDES 0x1060
|
||||
#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
|
||||
#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
|
||||
#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
|
||||
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
|
||||
#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
|
||||
#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
|
||||
#define E1000_DEV_ID_82572EI_COPPER 0x107D
|
||||
#define E1000_DEV_ID_82572EI_FIBER 0x107E
|
||||
#define E1000_DEV_ID_82572EI_SERDES 0x107F
|
||||
#define E1000_DEV_ID_82572EI 0x10B9
|
||||
#define E1000_DEV_ID_82573E 0x108B
|
||||
#define E1000_DEV_ID_82573E_IAMT 0x108C
|
||||
#define E1000_DEV_ID_82573L 0x109A
|
||||
#define E1000_DEV_ID_82574L 0x10D3
|
||||
#define E1000_DEV_ID_82574LA 0x10F6
|
||||
#define E1000_DEV_ID_82583V 0x150C
|
||||
|
||||
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
|
||||
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
|
||||
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
|
||||
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
|
||||
|
||||
#define E1000_DEV_ID_ICH8_82567V_3 0x1501
|
||||
#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
|
||||
#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
|
||||
#define E1000_DEV_ID_ICH8_IGP_C 0x104B
|
||||
#define E1000_DEV_ID_ICH8_IFE 0x104C
|
||||
#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
|
||||
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
|
||||
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
|
||||
#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
|
||||
#define E1000_DEV_ID_ICH9_BM 0x10E5
|
||||
#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
|
||||
#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
|
||||
#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
|
||||
#define E1000_DEV_ID_ICH9_IGP_C 0x294C
|
||||
#define E1000_DEV_ID_ICH9_IFE 0x10C0
|
||||
#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
|
||||
#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
|
||||
#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
|
||||
#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
|
||||
#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
|
||||
#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
|
||||
#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
|
||||
#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
|
||||
#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
|
||||
#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
|
||||
#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
|
||||
#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
|
||||
#define E1000_DEV_ID_PCH2_LV_LM 0x1502
|
||||
#define E1000_DEV_ID_PCH2_LV_V 0x1503
|
||||
|
||||
#define E1000_REVISION_4 4
|
||||
|
||||
#define E1000_FUNC_1 1
|
||||
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
|
||||
|
||||
enum e1000_mac_type {
|
||||
e1000_82571,
|
||||
e1000_82572,
|
||||
e1000_82573,
|
||||
e1000_82574,
|
||||
e1000_82583,
|
||||
e1000_80003es2lan,
|
||||
e1000_ich8lan,
|
||||
e1000_ich9lan,
|
||||
e1000_ich10lan,
|
||||
e1000_pchlan,
|
||||
e1000_pch2lan,
|
||||
};
|
||||
|
||||
enum e1000_media_type {
|
||||
e1000_media_type_unknown = 0,
|
||||
e1000_media_type_copper = 1,
|
||||
e1000_media_type_fiber = 2,
|
||||
e1000_media_type_internal_serdes = 3,
|
||||
e1000_num_media_types
|
||||
};
|
||||
|
||||
enum e1000_nvm_type {
|
||||
e1000_nvm_unknown = 0,
|
||||
e1000_nvm_none,
|
||||
e1000_nvm_eeprom_spi,
|
||||
e1000_nvm_flash_hw,
|
||||
e1000_nvm_flash_sw
|
||||
};
|
||||
|
||||
enum e1000_nvm_override {
|
||||
e1000_nvm_override_none = 0,
|
||||
e1000_nvm_override_spi_small,
|
||||
e1000_nvm_override_spi_large
|
||||
};
|
||||
|
||||
enum e1000_phy_type {
|
||||
e1000_phy_unknown = 0,
|
||||
e1000_phy_none,
|
||||
e1000_phy_m88,
|
||||
e1000_phy_igp,
|
||||
e1000_phy_igp_2,
|
||||
e1000_phy_gg82563,
|
||||
e1000_phy_igp_3,
|
||||
e1000_phy_ife,
|
||||
e1000_phy_bm,
|
||||
e1000_phy_82578,
|
||||
e1000_phy_82577,
|
||||
e1000_phy_82579,
|
||||
};
|
||||
|
||||
enum e1000_bus_width {
|
||||
e1000_bus_width_unknown = 0,
|
||||
e1000_bus_width_pcie_x1,
|
||||
e1000_bus_width_pcie_x2,
|
||||
e1000_bus_width_pcie_x4 = 4,
|
||||
e1000_bus_width_32,
|
||||
e1000_bus_width_64,
|
||||
e1000_bus_width_reserved
|
||||
};
|
||||
|
||||
enum e1000_1000t_rx_status {
|
||||
e1000_1000t_rx_status_not_ok = 0,
|
||||
e1000_1000t_rx_status_ok,
|
||||
e1000_1000t_rx_status_undefined = 0xFF
|
||||
};
|
||||
|
||||
enum e1000_rev_polarity{
|
||||
e1000_rev_polarity_normal = 0,
|
||||
e1000_rev_polarity_reversed,
|
||||
e1000_rev_polarity_undefined = 0xFF
|
||||
};
|
||||
|
||||
enum e1000_fc_mode {
|
||||
e1000_fc_none = 0,
|
||||
e1000_fc_rx_pause,
|
||||
e1000_fc_tx_pause,
|
||||
e1000_fc_full,
|
||||
e1000_fc_default = 0xFF
|
||||
};
|
||||
|
||||
enum e1000_ms_type {
|
||||
e1000_ms_hw_default = 0,
|
||||
e1000_ms_force_master,
|
||||
e1000_ms_force_slave,
|
||||
e1000_ms_auto
|
||||
};
|
||||
|
||||
enum e1000_smart_speed {
|
||||
e1000_smart_speed_default = 0,
|
||||
e1000_smart_speed_on,
|
||||
e1000_smart_speed_off
|
||||
};
|
||||
|
||||
enum e1000_serdes_link_state {
|
||||
e1000_serdes_link_down = 0,
|
||||
e1000_serdes_link_autoneg_progress,
|
||||
e1000_serdes_link_autoneg_complete,
|
||||
e1000_serdes_link_forced_up
|
||||
};
|
||||
|
||||
/* Receive Descriptor */
|
||||
struct e1000_rx_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
__le16 length; /* Length of data DMAed into data buffer */
|
||||
__le16 csum; /* Packet checksum */
|
||||
u8 status; /* Descriptor status */
|
||||
u8 errors; /* Descriptor Errors */
|
||||
__le16 special;
|
||||
};
|
||||
|
||||
/* Receive Descriptor - Extended */
|
||||
union e1000_rx_desc_extended {
|
||||
struct {
|
||||
__le64 buffer_addr;
|
||||
__le64 reserved;
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
__le32 mrq; /* Multiple Rx Queues */
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length;
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} upper;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
#define MAX_PS_BUFFERS 4
|
||||
/* Receive Descriptor - Packet Split */
|
||||
union e1000_rx_desc_packet_split {
|
||||
struct {
|
||||
/* one buffer for protocol header(s), three data buffers */
|
||||
__le64 buffer_addr[MAX_PS_BUFFERS];
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
__le32 mrq; /* Multiple Rx Queues */
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length0; /* length of buffer 0 */
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} middle;
|
||||
struct {
|
||||
__le16 header_status;
|
||||
__le16 length[3]; /* length of buffers 1-3 */
|
||||
} upper;
|
||||
__le64 reserved;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
/* Transmit Descriptor */
|
||||
struct e1000_tx_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le16 length; /* Data buffer length */
|
||||
u8 cso; /* Checksum offset */
|
||||
u8 cmd; /* Descriptor control */
|
||||
} flags;
|
||||
} lower;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
u8 status; /* Descriptor status */
|
||||
u8 css; /* Checksum start */
|
||||
__le16 special;
|
||||
} fields;
|
||||
} upper;
|
||||
};
|
||||
|
||||
/* Offload Context Descriptor */
|
||||
struct e1000_context_desc {
|
||||
union {
|
||||
__le32 ip_config;
|
||||
struct {
|
||||
u8 ipcss; /* IP checksum start */
|
||||
u8 ipcso; /* IP checksum offset */
|
||||
__le16 ipcse; /* IP checksum end */
|
||||
} ip_fields;
|
||||
} lower_setup;
|
||||
union {
|
||||
__le32 tcp_config;
|
||||
struct {
|
||||
u8 tucss; /* TCP checksum start */
|
||||
u8 tucso; /* TCP checksum offset */
|
||||
__le16 tucse; /* TCP checksum end */
|
||||
} tcp_fields;
|
||||
} upper_setup;
|
||||
__le32 cmd_and_length;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
u8 status; /* Descriptor status */
|
||||
u8 hdr_len; /* Header length */
|
||||
__le16 mss; /* Maximum segment size */
|
||||
} fields;
|
||||
} tcp_seg_setup;
|
||||
};
|
||||
|
||||
/* Offload data descriptor */
|
||||
struct e1000_data_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's buffer address */
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le16 length; /* Data buffer length */
|
||||
u8 typ_len_ext;
|
||||
u8 cmd;
|
||||
} flags;
|
||||
} lower;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
u8 status; /* Descriptor status */
|
||||
u8 popts; /* Packet Options */
|
||||
__le16 special; /* */
|
||||
} fields;
|
||||
} upper;
|
||||
};
|
||||
|
||||
/* Statistics counters collected by the MAC */
|
||||
struct e1000_hw_stats {
|
||||
u64 crcerrs;
|
||||
u64 algnerrc;
|
||||
u64 symerrs;
|
||||
u64 rxerrc;
|
||||
u64 mpc;
|
||||
u64 scc;
|
||||
u64 ecol;
|
||||
u64 mcc;
|
||||
u64 latecol;
|
||||
u64 colc;
|
||||
u64 dc;
|
||||
u64 tncrs;
|
||||
u64 sec;
|
||||
u64 cexterr;
|
||||
u64 rlec;
|
||||
u64 xonrxc;
|
||||
u64 xontxc;
|
||||
u64 xoffrxc;
|
||||
u64 xofftxc;
|
||||
u64 fcruc;
|
||||
u64 prc64;
|
||||
u64 prc127;
|
||||
u64 prc255;
|
||||
u64 prc511;
|
||||
u64 prc1023;
|
||||
u64 prc1522;
|
||||
u64 gprc;
|
||||
u64 bprc;
|
||||
u64 mprc;
|
||||
u64 gptc;
|
||||
u64 gorc;
|
||||
u64 gotc;
|
||||
u64 rnbc;
|
||||
u64 ruc;
|
||||
u64 rfc;
|
||||
u64 roc;
|
||||
u64 rjc;
|
||||
u64 mgprc;
|
||||
u64 mgpdc;
|
||||
u64 mgptc;
|
||||
u64 tor;
|
||||
u64 tot;
|
||||
u64 tpr;
|
||||
u64 tpt;
|
||||
u64 ptc64;
|
||||
u64 ptc127;
|
||||
u64 ptc255;
|
||||
u64 ptc511;
|
||||
u64 ptc1023;
|
||||
u64 ptc1522;
|
||||
u64 mptc;
|
||||
u64 bptc;
|
||||
u64 tsctc;
|
||||
u64 tsctfc;
|
||||
u64 iac;
|
||||
u64 icrxptc;
|
||||
u64 icrxatc;
|
||||
u64 ictxptc;
|
||||
u64 ictxatc;
|
||||
u64 ictxqec;
|
||||
u64 ictxqmtc;
|
||||
u64 icrxdmtc;
|
||||
u64 icrxoc;
|
||||
};
|
||||
|
||||
struct e1000_phy_stats {
|
||||
u32 idle_errors;
|
||||
u32 receive_errors;
|
||||
};
|
||||
|
||||
struct e1000_host_mng_dhcp_cookie {
|
||||
u32 signature;
|
||||
u8 status;
|
||||
u8 reserved0;
|
||||
u16 vlan_id;
|
||||
u32 reserved1;
|
||||
u16 reserved2;
|
||||
u8 reserved3;
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
/* Host Interface "Rev 1" */
|
||||
struct e1000_host_command_header {
|
||||
u8 command_id;
|
||||
u8 command_length;
|
||||
u8 command_options;
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
#define E1000_HI_MAX_DATA_LENGTH 252
|
||||
struct e1000_host_command_info {
|
||||
struct e1000_host_command_header command_header;
|
||||
u8 command_data[E1000_HI_MAX_DATA_LENGTH];
|
||||
};
|
||||
|
||||
/* Host Interface "Rev 2" */
|
||||
struct e1000_host_mng_command_header {
|
||||
u8 command_id;
|
||||
u8 checksum;
|
||||
u16 reserved1;
|
||||
u16 reserved2;
|
||||
u16 command_length;
|
||||
};
|
||||
|
||||
#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
|
||||
struct e1000_host_mng_command_info {
|
||||
struct e1000_host_mng_command_header command_header;
|
||||
u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
|
||||
};
|
||||
|
||||
/* Function pointers and static data for the MAC. */
|
||||
struct e1000_mac_operations {
|
||||
s32 (*id_led_init)(struct e1000_hw *);
|
||||
s32 (*blink_led)(struct e1000_hw *);
|
||||
bool (*check_mng_mode)(struct e1000_hw *);
|
||||
s32 (*check_for_link)(struct e1000_hw *);
|
||||
s32 (*cleanup_led)(struct e1000_hw *);
|
||||
void (*clear_hw_cntrs)(struct e1000_hw *);
|
||||
void (*clear_vfta)(struct e1000_hw *);
|
||||
s32 (*get_bus_info)(struct e1000_hw *);
|
||||
void (*set_lan_id)(struct e1000_hw *);
|
||||
s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
|
||||
s32 (*led_on)(struct e1000_hw *);
|
||||
s32 (*led_off)(struct e1000_hw *);
|
||||
void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
|
||||
s32 (*reset_hw)(struct e1000_hw *);
|
||||
s32 (*init_hw)(struct e1000_hw *);
|
||||
s32 (*setup_link)(struct e1000_hw *);
|
||||
s32 (*setup_physical_interface)(struct e1000_hw *);
|
||||
s32 (*setup_led)(struct e1000_hw *);
|
||||
void (*write_vfta)(struct e1000_hw *, u32, u32);
|
||||
s32 (*read_mac_addr)(struct e1000_hw *);
|
||||
};
|
||||
|
||||
/*
|
||||
* When to use various PHY register access functions:
|
||||
*
|
||||
* Func Caller
|
||||
* Function Does Does When to use
|
||||
* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
* X_reg L,P,A n/a for simple PHY reg accesses
|
||||
* X_reg_locked P,A L for multiple accesses of different regs
|
||||
* on different pages
|
||||
* X_reg_page A L,P for multiple accesses of different regs
|
||||
* on the same page
|
||||
*
|
||||
* Where X=[read|write], L=locking, P=sets page, A=register access
|
||||
*
|
||||
*/
|
||||
struct e1000_phy_operations {
|
||||
s32 (*acquire)(struct e1000_hw *);
|
||||
s32 (*cfg_on_link_up)(struct e1000_hw *);
|
||||
s32 (*check_polarity)(struct e1000_hw *);
|
||||
s32 (*check_reset_block)(struct e1000_hw *);
|
||||
s32 (*commit)(struct e1000_hw *);
|
||||
s32 (*force_speed_duplex)(struct e1000_hw *);
|
||||
s32 (*get_cfg_done)(struct e1000_hw *hw);
|
||||
s32 (*get_cable_length)(struct e1000_hw *);
|
||||
s32 (*get_info)(struct e1000_hw *);
|
||||
s32 (*set_page)(struct e1000_hw *, u16);
|
||||
s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
|
||||
s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
|
||||
s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
|
||||
void (*release)(struct e1000_hw *);
|
||||
s32 (*reset)(struct e1000_hw *);
|
||||
s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
|
||||
s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
|
||||
s32 (*write_reg)(struct e1000_hw *, u32, u16);
|
||||
s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
|
||||
s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
|
||||
void (*power_up)(struct e1000_hw *);
|
||||
void (*power_down)(struct e1000_hw *);
|
||||
};
|
||||
|
||||
/* Function pointers for the NVM. */
|
||||
struct e1000_nvm_operations {
|
||||
s32 (*acquire)(struct e1000_hw *);
|
||||
s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
|
||||
void (*release)(struct e1000_hw *);
|
||||
s32 (*update)(struct e1000_hw *);
|
||||
s32 (*valid_led_default)(struct e1000_hw *, u16 *);
|
||||
s32 (*validate)(struct e1000_hw *);
|
||||
s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
|
||||
};
|
||||
|
||||
struct e1000_mac_info {
|
||||
struct e1000_mac_operations ops;
|
||||
u8 addr[ETH_ALEN];
|
||||
u8 perm_addr[ETH_ALEN];
|
||||
|
||||
enum e1000_mac_type type;
|
||||
|
||||
u32 collision_delta;
|
||||
u32 ledctl_default;
|
||||
u32 ledctl_mode1;
|
||||
u32 ledctl_mode2;
|
||||
u32 mc_filter_type;
|
||||
u32 tx_packet_delta;
|
||||
u32 txcw;
|
||||
|
||||
u16 current_ifs_val;
|
||||
u16 ifs_max_val;
|
||||
u16 ifs_min_val;
|
||||
u16 ifs_ratio;
|
||||
u16 ifs_step_size;
|
||||
u16 mta_reg_count;
|
||||
|
||||
/* Maximum size of the MTA register table in all supported adapters */
|
||||
#define MAX_MTA_REG 128
|
||||
u32 mta_shadow[MAX_MTA_REG];
|
||||
u16 rar_entry_count;
|
||||
|
||||
u8 forced_speed_duplex;
|
||||
|
||||
bool adaptive_ifs;
|
||||
bool has_fwsm;
|
||||
bool arc_subsystem_valid;
|
||||
bool autoneg;
|
||||
bool autoneg_failed;
|
||||
bool get_link_status;
|
||||
bool in_ifs_mode;
|
||||
bool serdes_has_link;
|
||||
bool tx_pkt_filtering;
|
||||
enum e1000_serdes_link_state serdes_link_state;
|
||||
};
|
||||
|
||||
struct e1000_phy_info {
|
||||
struct e1000_phy_operations ops;
|
||||
|
||||
enum e1000_phy_type type;
|
||||
|
||||
enum e1000_1000t_rx_status local_rx;
|
||||
enum e1000_1000t_rx_status remote_rx;
|
||||
enum e1000_ms_type ms_type;
|
||||
enum e1000_ms_type original_ms_type;
|
||||
enum e1000_rev_polarity cable_polarity;
|
||||
enum e1000_smart_speed smart_speed;
|
||||
|
||||
u32 addr;
|
||||
u32 id;
|
||||
u32 reset_delay_us; /* in usec */
|
||||
u32 revision;
|
||||
|
||||
enum e1000_media_type media_type;
|
||||
|
||||
u16 autoneg_advertised;
|
||||
u16 autoneg_mask;
|
||||
u16 cable_length;
|
||||
u16 max_cable_length;
|
||||
u16 min_cable_length;
|
||||
|
||||
u8 mdix;
|
||||
|
||||
bool disable_polarity_correction;
|
||||
bool is_mdix;
|
||||
bool polarity_correction;
|
||||
bool speed_downgraded;
|
||||
bool autoneg_wait_to_complete;
|
||||
};
|
||||
|
||||
struct e1000_nvm_info {
|
||||
struct e1000_nvm_operations ops;
|
||||
|
||||
enum e1000_nvm_type type;
|
||||
enum e1000_nvm_override override;
|
||||
|
||||
u32 flash_bank_size;
|
||||
u32 flash_base_addr;
|
||||
|
||||
u16 word_size;
|
||||
u16 delay_usec;
|
||||
u16 address_bits;
|
||||
u16 opcode_bits;
|
||||
u16 page_size;
|
||||
};
|
||||
|
||||
struct e1000_bus_info {
|
||||
enum e1000_bus_width width;
|
||||
|
||||
u16 func;
|
||||
};
|
||||
|
||||
struct e1000_fc_info {
|
||||
u32 high_water; /* Flow control high-water mark */
|
||||
u32 low_water; /* Flow control low-water mark */
|
||||
u16 pause_time; /* Flow control pause timer */
|
||||
u16 refresh_time; /* Flow control refresh timer */
|
||||
bool send_xon; /* Flow control send XON */
|
||||
bool strict_ieee; /* Strict IEEE mode */
|
||||
enum e1000_fc_mode current_mode; /* FC mode in effect */
|
||||
enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
|
||||
};
|
||||
|
||||
struct e1000_dev_spec_82571 {
|
||||
bool laa_is_present;
|
||||
u32 smb_counter;
|
||||
};
|
||||
|
||||
struct e1000_dev_spec_80003es2lan {
|
||||
bool mdic_wa_enable;
|
||||
};
|
||||
|
||||
struct e1000_shadow_ram {
|
||||
u16 value;
|
||||
bool modified;
|
||||
};
|
||||
|
||||
#define E1000_ICH8_SHADOW_RAM_WORDS 2048
|
||||
|
||||
struct e1000_dev_spec_ich8lan {
|
||||
bool kmrn_lock_loss_workaround_enabled;
|
||||
struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
|
||||
bool nvm_k1_enabled;
|
||||
bool eee_disable;
|
||||
};
|
||||
|
||||
struct e1000_hw {
|
||||
struct e1000_adapter *adapter;
|
||||
|
||||
u8 __iomem *hw_addr;
|
||||
u8 __iomem *flash_address;
|
||||
|
||||
struct e1000_mac_info mac;
|
||||
struct e1000_fc_info fc;
|
||||
struct e1000_phy_info phy;
|
||||
struct e1000_nvm_info nvm;
|
||||
struct e1000_bus_info bus;
|
||||
struct e1000_host_mng_dhcp_cookie mng_cookie;
|
||||
|
||||
union {
|
||||
struct e1000_dev_spec_82571 e82571;
|
||||
struct e1000_dev_spec_80003es2lan e80003es2lan;
|
||||
struct e1000_dev_spec_ich8lan ich8lan;
|
||||
} dev_spec;
|
||||
};
|
||||
|
||||
#endif
|
||||
4111
drivers/net/ethernet/intel/e1000e/ich8lan.c
Normal file
4111
drivers/net/ethernet/intel/e1000e/ich8lan.c
Normal file
File diff suppressed because it is too large
Load Diff
2692
drivers/net/ethernet/intel/e1000e/lib.c
Normal file
2692
drivers/net/ethernet/intel/e1000e/lib.c
Normal file
File diff suppressed because it is too large
Load Diff
6312
drivers/net/ethernet/intel/e1000e/netdev.c
Normal file
6312
drivers/net/ethernet/intel/e1000e/netdev.c
Normal file
File diff suppressed because it is too large
Load Diff
478
drivers/net/ethernet/intel/e1000e/param.c
Normal file
478
drivers/net/ethernet/intel/e1000e/param.c
Normal file
@@ -0,0 +1,478 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Intel PRO/1000 Linux driver
|
||||
Copyright(c) 1999 - 2011 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
Linux NICS <linux.nics@intel.com>
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include "e1000.h"
|
||||
|
||||
/*
|
||||
* This is the only thing that needs to be changed to adjust the
|
||||
* maximum number of ports that the driver can manage.
|
||||
*/
|
||||
|
||||
#define E1000_MAX_NIC 32
|
||||
|
||||
#define OPTION_UNSET -1
|
||||
#define OPTION_DISABLED 0
|
||||
#define OPTION_ENABLED 1
|
||||
|
||||
#define COPYBREAK_DEFAULT 256
|
||||
unsigned int copybreak = COPYBREAK_DEFAULT;
|
||||
module_param(copybreak, uint, 0644);
|
||||
MODULE_PARM_DESC(copybreak,
|
||||
"Maximum size of packet that is copied to a new buffer on receive");
|
||||
|
||||
/*
|
||||
* All parameters are treated the same, as an integer array of values.
|
||||
* This macro just reduces the need to repeat the same declaration code
|
||||
* over and over (plus this helps to avoid typo bugs).
|
||||
*/
|
||||
|
||||
#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
|
||||
#define E1000_PARAM(X, desc) \
|
||||
static int __devinitdata X[E1000_MAX_NIC+1] \
|
||||
= E1000_PARAM_INIT; \
|
||||
static unsigned int num_##X; \
|
||||
module_param_array_named(X, X, int, &num_##X, 0); \
|
||||
MODULE_PARM_DESC(X, desc);
|
||||
|
||||
/*
|
||||
* Transmit Interrupt Delay in units of 1.024 microseconds
|
||||
* Tx interrupt delay needs to typically be set to something non-zero
|
||||
*
|
||||
* Valid Range: 0-65535
|
||||
*/
|
||||
E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
|
||||
#define DEFAULT_TIDV 8
|
||||
#define MAX_TXDELAY 0xFFFF
|
||||
#define MIN_TXDELAY 0
|
||||
|
||||
/*
|
||||
* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
|
||||
*
|
||||
* Valid Range: 0-65535
|
||||
*/
|
||||
E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
|
||||
#define DEFAULT_TADV 32
|
||||
#define MAX_TXABSDELAY 0xFFFF
|
||||
#define MIN_TXABSDELAY 0
|
||||
|
||||
/*
|
||||
* Receive Interrupt Delay in units of 1.024 microseconds
|
||||
* hardware will likely hang if you set this to anything but zero.
|
||||
*
|
||||
* Valid Range: 0-65535
|
||||
*/
|
||||
E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
|
||||
#define MAX_RXDELAY 0xFFFF
|
||||
#define MIN_RXDELAY 0
|
||||
|
||||
/*
|
||||
* Receive Absolute Interrupt Delay in units of 1.024 microseconds
|
||||
*
|
||||
* Valid Range: 0-65535
|
||||
*/
|
||||
E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
|
||||
#define MAX_RXABSDELAY 0xFFFF
|
||||
#define MIN_RXABSDELAY 0
|
||||
|
||||
/*
|
||||
* Interrupt Throttle Rate (interrupts/sec)
|
||||
*
|
||||
* Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
|
||||
*/
|
||||
E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
|
||||
#define DEFAULT_ITR 3
|
||||
#define MAX_ITR 100000
|
||||
#define MIN_ITR 100
|
||||
|
||||
/* IntMode (Interrupt Mode)
|
||||
*
|
||||
* Valid Range: 0 - 2
|
||||
*
|
||||
* Default Value: 2 (MSI-X)
|
||||
*/
|
||||
E1000_PARAM(IntMode, "Interrupt Mode");
|
||||
#define MAX_INTMODE 2
|
||||
#define MIN_INTMODE 0
|
||||
|
||||
/*
|
||||
* Enable Smart Power Down of the PHY
|
||||
*
|
||||
* Valid Range: 0, 1
|
||||
*
|
||||
* Default Value: 0 (disabled)
|
||||
*/
|
||||
E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
|
||||
|
||||
/*
|
||||
* Enable Kumeran Lock Loss workaround
|
||||
*
|
||||
* Valid Range: 0, 1
|
||||
*
|
||||
* Default Value: 1 (enabled)
|
||||
*/
|
||||
E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
|
||||
|
||||
/*
|
||||
* Write Protect NVM
|
||||
*
|
||||
* Valid Range: 0, 1
|
||||
*
|
||||
* Default Value: 1 (enabled)
|
||||
*/
|
||||
E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]");
|
||||
|
||||
/*
|
||||
* Enable CRC Stripping
|
||||
*
|
||||
* Valid Range: 0, 1
|
||||
*
|
||||
* Default Value: 1 (enabled)
|
||||
*/
|
||||
E1000_PARAM(CrcStripping, "Enable CRC Stripping, disable if your BMC needs " \
|
||||
"the CRC");
|
||||
|
||||
struct e1000_option {
|
||||
enum { enable_option, range_option, list_option } type;
|
||||
const char *name;
|
||||
const char *err;
|
||||
int def;
|
||||
union {
|
||||
struct { /* range_option info */
|
||||
int min;
|
||||
int max;
|
||||
} r;
|
||||
struct { /* list_option info */
|
||||
int nr;
|
||||
struct e1000_opt_list { int i; char *str; } *p;
|
||||
} l;
|
||||
} arg;
|
||||
};
|
||||
|
||||
static int __devinit e1000_validate_option(unsigned int *value,
|
||||
const struct e1000_option *opt,
|
||||
struct e1000_adapter *adapter)
|
||||
{
|
||||
if (*value == OPTION_UNSET) {
|
||||
*value = opt->def;
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (opt->type) {
|
||||
case enable_option:
|
||||
switch (*value) {
|
||||
case OPTION_ENABLED:
|
||||
e_info("%s Enabled\n", opt->name);
|
||||
return 0;
|
||||
case OPTION_DISABLED:
|
||||
e_info("%s Disabled\n", opt->name);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case range_option:
|
||||
if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
|
||||
e_info("%s set to %i\n", opt->name, *value);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case list_option: {
|
||||
int i;
|
||||
struct e1000_opt_list *ent;
|
||||
|
||||
for (i = 0; i < opt->arg.l.nr; i++) {
|
||||
ent = &opt->arg.l.p[i];
|
||||
if (*value == ent->i) {
|
||||
if (ent->str[0] != '\0')
|
||||
e_info("%s\n", ent->str);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
e_info("Invalid %s value specified (%i) %s\n", opt->name, *value,
|
||||
opt->err);
|
||||
*value = opt->def;
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000e_check_options - Range Checking for Command Line Parameters
|
||||
* @adapter: board private structure
|
||||
*
|
||||
* This routine checks all command line parameters for valid user
|
||||
* input. If an invalid value is given, or if no user specified
|
||||
* value exists, a default value is used. The final value is stored
|
||||
* in a variable in the adapter structure.
|
||||
**/
|
||||
void __devinit e1000e_check_options(struct e1000_adapter *adapter)
|
||||
{
|
||||
struct e1000_hw *hw = &adapter->hw;
|
||||
int bd = adapter->bd_number;
|
||||
|
||||
if (bd >= E1000_MAX_NIC) {
|
||||
e_notice("Warning: no configuration for board #%i\n", bd);
|
||||
e_notice("Using defaults for all values\n");
|
||||
}
|
||||
|
||||
{ /* Transmit Interrupt Delay */
|
||||
static const struct e1000_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Transmit Interrupt Delay",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_TIDV),
|
||||
.def = DEFAULT_TIDV,
|
||||
.arg = { .r = { .min = MIN_TXDELAY,
|
||||
.max = MAX_TXDELAY } }
|
||||
};
|
||||
|
||||
if (num_TxIntDelay > bd) {
|
||||
adapter->tx_int_delay = TxIntDelay[bd];
|
||||
e1000_validate_option(&adapter->tx_int_delay, &opt,
|
||||
adapter);
|
||||
} else {
|
||||
adapter->tx_int_delay = opt.def;
|
||||
}
|
||||
}
|
||||
{ /* Transmit Absolute Interrupt Delay */
|
||||
static const struct e1000_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Transmit Absolute Interrupt Delay",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_TADV),
|
||||
.def = DEFAULT_TADV,
|
||||
.arg = { .r = { .min = MIN_TXABSDELAY,
|
||||
.max = MAX_TXABSDELAY } }
|
||||
};
|
||||
|
||||
if (num_TxAbsIntDelay > bd) {
|
||||
adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
|
||||
e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
|
||||
adapter);
|
||||
} else {
|
||||
adapter->tx_abs_int_delay = opt.def;
|
||||
}
|
||||
}
|
||||
{ /* Receive Interrupt Delay */
|
||||
static struct e1000_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Receive Interrupt Delay",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_RDTR),
|
||||
.def = DEFAULT_RDTR,
|
||||
.arg = { .r = { .min = MIN_RXDELAY,
|
||||
.max = MAX_RXDELAY } }
|
||||
};
|
||||
|
||||
if (num_RxIntDelay > bd) {
|
||||
adapter->rx_int_delay = RxIntDelay[bd];
|
||||
e1000_validate_option(&adapter->rx_int_delay, &opt,
|
||||
adapter);
|
||||
} else {
|
||||
adapter->rx_int_delay = opt.def;
|
||||
}
|
||||
}
|
||||
{ /* Receive Absolute Interrupt Delay */
|
||||
static const struct e1000_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Receive Absolute Interrupt Delay",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_RADV),
|
||||
.def = DEFAULT_RADV,
|
||||
.arg = { .r = { .min = MIN_RXABSDELAY,
|
||||
.max = MAX_RXABSDELAY } }
|
||||
};
|
||||
|
||||
if (num_RxAbsIntDelay > bd) {
|
||||
adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
|
||||
e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
|
||||
adapter);
|
||||
} else {
|
||||
adapter->rx_abs_int_delay = opt.def;
|
||||
}
|
||||
}
|
||||
{ /* Interrupt Throttling Rate */
|
||||
static const struct e1000_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Interrupt Throttling Rate (ints/sec)",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_ITR),
|
||||
.def = DEFAULT_ITR,
|
||||
.arg = { .r = { .min = MIN_ITR,
|
||||
.max = MAX_ITR } }
|
||||
};
|
||||
|
||||
if (num_InterruptThrottleRate > bd) {
|
||||
adapter->itr = InterruptThrottleRate[bd];
|
||||
switch (adapter->itr) {
|
||||
case 0:
|
||||
e_info("%s turned off\n", opt.name);
|
||||
break;
|
||||
case 1:
|
||||
e_info("%s set to dynamic mode\n", opt.name);
|
||||
adapter->itr_setting = adapter->itr;
|
||||
adapter->itr = 20000;
|
||||
break;
|
||||
case 3:
|
||||
e_info("%s set to dynamic conservative mode\n",
|
||||
opt.name);
|
||||
adapter->itr_setting = adapter->itr;
|
||||
adapter->itr = 20000;
|
||||
break;
|
||||
case 4:
|
||||
e_info("%s set to simplified (2000-8000 ints) "
|
||||
"mode\n", opt.name);
|
||||
adapter->itr_setting = 4;
|
||||
break;
|
||||
default:
|
||||
/*
|
||||
* Save the setting, because the dynamic bits
|
||||
* change itr.
|
||||
*/
|
||||
if (e1000_validate_option(&adapter->itr, &opt,
|
||||
adapter) &&
|
||||
(adapter->itr == 3)) {
|
||||
/*
|
||||
* In case of invalid user value,
|
||||
* default to conservative mode.
|
||||
*/
|
||||
adapter->itr_setting = adapter->itr;
|
||||
adapter->itr = 20000;
|
||||
} else {
|
||||
/*
|
||||
* Clear the lower two bits because
|
||||
* they are used as control.
|
||||
*/
|
||||
adapter->itr_setting =
|
||||
adapter->itr & ~3;
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
adapter->itr_setting = opt.def;
|
||||
adapter->itr = 20000;
|
||||
}
|
||||
}
|
||||
{ /* Interrupt Mode */
|
||||
static struct e1000_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Interrupt Mode",
|
||||
.err = "defaulting to 2 (MSI-X)",
|
||||
.def = E1000E_INT_MODE_MSIX,
|
||||
.arg = { .r = { .min = MIN_INTMODE,
|
||||
.max = MAX_INTMODE } }
|
||||
};
|
||||
|
||||
if (num_IntMode > bd) {
|
||||
unsigned int int_mode = IntMode[bd];
|
||||
e1000_validate_option(&int_mode, &opt, adapter);
|
||||
adapter->int_mode = int_mode;
|
||||
} else {
|
||||
adapter->int_mode = opt.def;
|
||||
}
|
||||
}
|
||||
{ /* Smart Power Down */
|
||||
static const struct e1000_option opt = {
|
||||
.type = enable_option,
|
||||
.name = "PHY Smart Power Down",
|
||||
.err = "defaulting to Disabled",
|
||||
.def = OPTION_DISABLED
|
||||
};
|
||||
|
||||
if (num_SmartPowerDownEnable > bd) {
|
||||
unsigned int spd = SmartPowerDownEnable[bd];
|
||||
e1000_validate_option(&spd, &opt, adapter);
|
||||
if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN)
|
||||
&& spd)
|
||||
adapter->flags |= FLAG_SMART_POWER_DOWN;
|
||||
}
|
||||
}
|
||||
{ /* CRC Stripping */
|
||||
static const struct e1000_option opt = {
|
||||
.type = enable_option,
|
||||
.name = "CRC Stripping",
|
||||
.err = "defaulting to Enabled",
|
||||
.def = OPTION_ENABLED
|
||||
};
|
||||
|
||||
if (num_CrcStripping > bd) {
|
||||
unsigned int crc_stripping = CrcStripping[bd];
|
||||
e1000_validate_option(&crc_stripping, &opt, adapter);
|
||||
if (crc_stripping == OPTION_ENABLED)
|
||||
adapter->flags2 |= FLAG2_CRC_STRIPPING;
|
||||
} else {
|
||||
adapter->flags2 |= FLAG2_CRC_STRIPPING;
|
||||
}
|
||||
}
|
||||
{ /* Kumeran Lock Loss Workaround */
|
||||
static const struct e1000_option opt = {
|
||||
.type = enable_option,
|
||||
.name = "Kumeran Lock Loss Workaround",
|
||||
.err = "defaulting to Enabled",
|
||||
.def = OPTION_ENABLED
|
||||
};
|
||||
|
||||
if (num_KumeranLockLoss > bd) {
|
||||
unsigned int kmrn_lock_loss = KumeranLockLoss[bd];
|
||||
e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
|
||||
if (hw->mac.type == e1000_ich8lan)
|
||||
e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw,
|
||||
kmrn_lock_loss);
|
||||
} else {
|
||||
if (hw->mac.type == e1000_ich8lan)
|
||||
e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw,
|
||||
opt.def);
|
||||
}
|
||||
}
|
||||
{ /* Write-protect NVM */
|
||||
static const struct e1000_option opt = {
|
||||
.type = enable_option,
|
||||
.name = "Write-protect NVM",
|
||||
.err = "defaulting to Enabled",
|
||||
.def = OPTION_ENABLED
|
||||
};
|
||||
|
||||
if (adapter->flags & FLAG_IS_ICH) {
|
||||
if (num_WriteProtectNVM > bd) {
|
||||
unsigned int write_protect_nvm = WriteProtectNVM[bd];
|
||||
e1000_validate_option(&write_protect_nvm, &opt,
|
||||
adapter);
|
||||
if (write_protect_nvm)
|
||||
adapter->flags |= FLAG_READ_ONLY_NVM;
|
||||
} else {
|
||||
if (opt.def)
|
||||
adapter->flags |= FLAG_READ_ONLY_NVM;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
3377
drivers/net/ethernet/intel/e1000e/phy.c
Normal file
3377
drivers/net/ethernet/intel/e1000e/phy.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user