Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull locking/atomics update from Thomas Gleixner: "The locking, atomics and memory model brains delivered: - A larger update to the atomics code which reworks the ordering barriers, consolidates the atomic primitives, provides the new atomic64_fetch_add_unless() primitive and cleans up the include hell. - Simplify cmpxchg() instrumentation and add instrumentation for xchg() and cmpxchg_double(). - Updates to the memory model and documentation" * 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (48 commits) locking/atomics: Rework ordering barriers locking/atomics: Instrument cmpxchg_double*() locking/atomics: Instrument xchg() locking/atomics: Simplify cmpxchg() instrumentation locking/atomics/x86: Reduce arch_cmpxchg64*() instrumentation tools/memory-model: Rename litmus tests to comply to norm7 tools/memory-model/Documentation: Fix typo, smb->smp sched/Documentation: Update wake_up() & co. memory-barrier guarantees locking/spinlock, sched/core: Clarify requirements for smp_mb__after_spinlock() sched/core: Use smp_mb() in wake_woken_function() tools/memory-model: Add informal LKMM documentation to MAINTAINERS locking/atomics/Documentation: Describe atomic_set() as a write operation tools/memory-model: Make scripts executable tools/memory-model: Remove ACCESS_ONCE() from model tools/memory-model: Remove ACCESS_ONCE() from recipes locking/memory-barriers.txt/kokr: Update Korean translation to fix broken DMA vs. MMIO ordering example MAINTAINERS: Add Daniel Lustig as an LKMM reviewer tools/memory-model: Fix ISA2+pooncelock+pooncelock+pombonce name tools/memory-model: Add litmus test for full multicopy atomicity locking/refcount: Always allow checked forms ...
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@@ -126,11 +126,13 @@ static inline void atomic_inc(atomic_t *v)
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{
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__asm__ __volatile__("addql #1,%0" : "+m" (*v));
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}
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#define atomic_inc atomic_inc
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static inline void atomic_dec(atomic_t *v)
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{
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__asm__ __volatile__("subql #1,%0" : "+m" (*v));
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}
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#define atomic_dec atomic_dec
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static inline int atomic_dec_and_test(atomic_t *v)
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{
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@@ -138,6 +140,7 @@ static inline int atomic_dec_and_test(atomic_t *v)
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__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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return c != 0;
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}
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#define atomic_dec_and_test atomic_dec_and_test
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static inline int atomic_dec_and_test_lt(atomic_t *v)
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{
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@@ -155,6 +158,7 @@ static inline int atomic_inc_and_test(atomic_t *v)
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__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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return c != 0;
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}
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#define atomic_inc_and_test atomic_inc_and_test
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#ifdef CONFIG_RMW_INSNS
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@@ -190,9 +194,6 @@ static inline int atomic_xchg(atomic_t *v, int new)
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#endif /* !CONFIG_RMW_INSNS */
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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static inline int atomic_sub_and_test(int i, atomic_t *v)
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{
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char c;
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@@ -201,6 +202,7 @@ static inline int atomic_sub_and_test(int i, atomic_t *v)
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: ASM_DI (i));
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return c != 0;
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}
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#define atomic_sub_and_test atomic_sub_and_test
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static inline int atomic_add_negative(int i, atomic_t *v)
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{
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@@ -210,20 +212,6 @@ static inline int atomic_add_negative(int i, atomic_t *v)
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: ASM_DI (i));
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return c != 0;
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}
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static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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for (;;) {
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if (unlikely(c == (u)))
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break;
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old = atomic_cmpxchg((v), c, c + (a));
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if (likely(old == c))
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break;
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c = old;
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}
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return c;
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}
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#define atomic_add_negative atomic_add_negative
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#endif /* __ARCH_M68K_ATOMIC __ */
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@@ -519,12 +519,16 @@ static inline int __fls(int x)
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#endif
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/* Simple test-and-set bit locks */
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#define test_and_set_bit_lock test_and_set_bit
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#define clear_bit_unlock clear_bit
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#define __clear_bit_unlock clear_bit_unlock
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#include <asm-generic/bitops/ext2-atomic.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#endif /* __KERNEL__ */
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#endif /* _M68K_BITOPS_H */
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