drm/radeon: enforce use of radeon_get_ib_value when reading user cmd
When ever parsing cmd buffer supplied by userspace we need to use radeon_get_ib_value rather than directly accessing the ib as the user cmd might not yet be copied into the ib thus the parser might read value that does not correspond to what user is sending and possibly allowing user to send malicious command undected. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie

parent
e28f639eea
commit
de0babd60d
@@ -2623,14 +2623,14 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
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return -EINVAL;
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}
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if (tiled) {
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dst_offset = ib[idx+1];
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dst_offset = radeon_get_ib_value(p, idx+1);
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dst_offset <<= 8;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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p->idx += count + 5;
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} else {
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dst_offset = ib[idx+1];
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dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
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dst_offset = radeon_get_ib_value(p, idx+1);
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dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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@@ -2658,32 +2658,32 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
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/* detile bit */
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if (idx_value & (1 << 31)) {
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/* tiled src, linear dst */
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src_offset = ib[idx+1];
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src_offset = radeon_get_ib_value(p, idx+1);
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src_offset <<= 8;
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ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
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dst_offset = ib[idx+5];
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dst_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
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dst_offset = radeon_get_ib_value(p, idx+5);
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dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
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ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
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} else {
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/* linear src, tiled dst */
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src_offset = ib[idx+5];
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src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
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src_offset = radeon_get_ib_value(p, idx+5);
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src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
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ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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dst_offset = ib[idx+1];
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dst_offset = radeon_get_ib_value(p, idx+1);
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dst_offset <<= 8;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
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}
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p->idx += 7;
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} else {
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if (p->family >= CHIP_RV770) {
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src_offset = ib[idx+2];
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src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
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dst_offset = ib[idx+1];
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dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
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src_offset = radeon_get_ib_value(p, idx+2);
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src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
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dst_offset = radeon_get_ib_value(p, idx+1);
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dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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@@ -2691,10 +2691,10 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
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ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
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p->idx += 5;
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} else {
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src_offset = ib[idx+2];
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src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
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dst_offset = ib[idx+1];
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dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
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src_offset = radeon_get_ib_value(p, idx+2);
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src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
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dst_offset = radeon_get_ib_value(p, idx+1);
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dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
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ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
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ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
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@@ -2724,8 +2724,8 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
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DRM_ERROR("bad DMA_PACKET_WRITE\n");
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return -EINVAL;
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}
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dst_offset = ib[idx+1];
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dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
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dst_offset = radeon_get_ib_value(p, idx+1);
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dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
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if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
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dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
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dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
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