x86, cpu: Detect more TLB configuration
The Intel Software Developer’s Manual covers few more TLB configurations exposed as CPUID 2 descriptors: 61H Instruction TLB: 4 KByte pages, fully associative, 48 entries 63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries 76H Instruction TLB: 2M/4M pages, fully associative, 8 entries B5H Instruction TLB: 4KByte pages, 8-way set associative, 64 entries B6H Instruction TLB: 4KByte pages, 8-way set associative, 128 entries C1H Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries C2H DTLB DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries Let's detect them as well. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Link: http://lkml.kernel.org/r/1387801018-14499-1-git-send-email-kirill.shutemov@linux.intel.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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H. Peter Anvin

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@@ -472,6 +472,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO];
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u16 __read_mostly tlb_lld_4k[NR_INFO];
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u16 __read_mostly tlb_lld_2m[NR_INFO];
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u16 __read_mostly tlb_lld_4m[NR_INFO];
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u16 __read_mostly tlb_lld_1g[NR_INFO];
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/*
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* tlb_flushall_shift shows the balance point in replacing cr3 write
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@@ -486,13 +487,13 @@ void cpu_detect_tlb(struct cpuinfo_x86 *c)
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if (this_cpu->c_detect_tlb)
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this_cpu->c_detect_tlb(c);
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printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
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"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
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printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
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"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
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"tlb_flushall_shift: %d\n",
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tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
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tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
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tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
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tlb_flushall_shift);
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tlb_lld_1g[ENTRIES], tlb_flushall_shift);
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}
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void detect_ht(struct cpuinfo_x86 *c)
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