[SPARC64]: Add a secondary TSB for hugepage mappings.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
committed by
David S. Miller
David S. Miller
parent
14778d9072
commit
dcc1e8dd88
@@ -3,8 +3,13 @@
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <linux/config.h>
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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#include <asm/page.h>
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#include <asm/cpudata.h>
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#include <asm/mmu.h>
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.text
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.align 32
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@@ -34,34 +39,124 @@ tsb_miss_itlb:
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ldxa [%g4] ASI_IMMU, %g4
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g1 -- PAGE_SIZE TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g4 -- missing virtual address
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* %g6 -- TAG TARGET (vaddr >> 22)
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*/
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tsb_miss_page_table_walk:
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TRAP_LOAD_PGD_PHYS(%g7, %g5)
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TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
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/* And now we have the PGD base physical address in %g7. */
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tsb_miss_page_table_walk_sun4v_fastpath:
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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/* Before committing to a full page table walk,
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* check the huge page TSB.
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*/
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#ifdef CONFIG_HUGETLB_PAGE
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661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
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nop
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov SCRATCHPAD_UTSBREG2, %g5
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ldxa [%g5] ASI_SCRATCHPAD, %g5
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.previous
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cmp %g5, -1
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be,pt %xcc, 80f
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nop
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/* We need an aligned pair of registers containing 2 values
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* which can be easily rematerialized. %g6 and %g7 foot the
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* bill just nicely. We'll save %g6 away into %g2 for the
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* huge page TSB TAG comparison.
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*
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* Perform a huge page TSB lookup.
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*/
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mov %g6, %g2
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and %g5, 0x7, %g6
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mov 512, %g7
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andn %g5, 0x7, %g5
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sllx %g7, %g6, %g7
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srlx %g4, HPAGE_SHIFT, %g6
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sub %g7, 1, %g7
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and %g6, %g7, %g6
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sllx %g6, 4, %g6
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add %g5, %g6, %g5
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TSB_LOAD_QUAD(%g5, %g6)
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cmp %g6, %g2
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be,a,pt %xcc, tsb_tlb_reload
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mov %g7, %g5
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/* No match, remember the huge page TSB entry address,
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* and restore %g6 and %g7.
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*/
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TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
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srlx %g4, 22, %g6
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80: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
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#endif
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ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g5 -- physical address of PTE in Linux page tables
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* %g4 -- missing virtual address
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* %g6 -- TAG TARGET (vaddr >> 22)
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* %g7 -- page table physical address
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*
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* We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
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* TSB both lack a matching entry.
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*/
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tsb_miss_page_table_walk_sun4v_fastpath:
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,pn %g5, tsb_do_fault
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nop
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#ifdef CONFIG_HUGETLB_PAGE
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661: sethi %uhi(_PAGE_SZALL_4U), %g7
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sllx %g7, 32, %g7
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov _PAGE_SZALL_4V, %g7
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nop
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.previous
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and %g5, %g7, %g2
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661: sethi %uhi(_PAGE_SZHUGE_4U), %g7
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sllx %g7, 32, %g7
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov _PAGE_SZHUGE_4V, %g7
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nop
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.previous
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cmp %g2, %g7
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bne,pt %xcc, 60f
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nop
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/* It is a huge page, use huge page TSB entry address we
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* calculated above.
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*/
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TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
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ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g2
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cmp %g2, -1
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movne %xcc, %g2, %g1
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60:
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#endif
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g5 -- valid PTE
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* %g6 -- TAG TARGET (vaddr >> 22)
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*/
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tsb_reload:
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TSB_LOCK_TAG(%g1, %g2, %g7)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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mov 1, %g7
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sllx %g7, TSB_TAG_INVALID_BIT, %g7
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brgez,a,pn %g5, tsb_do_fault
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TSB_STORE(%g1, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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/* Finally, load TLB and return from trap. */
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@@ -240,10 +335,9 @@ tsb_flush:
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* schedule() time.
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*
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* %o0: page table physical address
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* %o1: TSB register value
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* %o2: TSB virtual address
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* %o3: TSB mapping locked PTE
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* %o4: Hypervisor TSB descriptor physical address
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* %o1: TSB base config pointer
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* %o2: TSB huge config pointer, or NULL if none
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* %o3: Hypervisor TSB descriptor physical address
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*
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* We have to run this whole thing with interrupts
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* disabled so that the current cpu doesn't change
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@@ -253,63 +347,79 @@ tsb_flush:
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.globl __tsb_context_switch
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.type __tsb_context_switch,#function
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__tsb_context_switch:
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rdpr %pstate, %o5
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wrpr %o5, PSTATE_IE, %pstate
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rdpr %pstate, %g1
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wrpr %g1, PSTATE_IE, %pstate
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TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
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ldub [%g6 + TI_CPU], %g1
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sethi %hi(trap_block), %g2
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sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
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or %g2, %lo(trap_block), %g2
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add %g2, %g1, %g2
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stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
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sethi %hi(tlb_type), %g1
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lduw [%g1 + %lo(tlb_type)], %g1
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cmp %g1, 3
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bne,pt %icc, 1f
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ldx [%o1 + TSB_CONFIG_REG_VAL], %o0
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brz,pt %o2, 1f
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mov -1, %g3
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ldx [%o2 + TSB_CONFIG_REG_VAL], %g3
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1: stx %g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]
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sethi %hi(tlb_type), %g2
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lduw [%g2 + %lo(tlb_type)], %g2
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cmp %g2, 3
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bne,pt %icc, 50f
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nop
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/* Hypervisor TSB switch. */
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mov SCRATCHPAD_UTSBREG1, %g1
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stxa %o1, [%g1] ASI_SCRATCHPAD
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mov -1, %g2
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mov SCRATCHPAD_UTSBREG2, %g1
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stxa %g2, [%g1] ASI_SCRATCHPAD
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mov SCRATCHPAD_UTSBREG1, %o5
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stxa %o0, [%o5] ASI_SCRATCHPAD
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mov SCRATCHPAD_UTSBREG2, %o5
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stxa %g3, [%o5] ASI_SCRATCHPAD
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/* Save away %o5's %pstate, we have to use %o5 for
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* the hypervisor call.
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*/
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mov %o5, %g1
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mov 2, %o0
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cmp %g3, -1
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move %xcc, 1, %o0
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mov HV_FAST_MMU_TSB_CTXNON0, %o5
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mov 1, %o0
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mov %o4, %o1
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mov %o3, %o1
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ta HV_FAST_TRAP
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/* Finish up and restore %o5. */
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/* Finish up. */
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ba,pt %xcc, 9f
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mov %g1, %o5
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/* SUN4U TSB switch. */
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1: mov TSB_REG, %g1
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stxa %o1, [%g1] ASI_DMMU
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membar #Sync
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stxa %o1, [%g1] ASI_IMMU
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membar #Sync
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2: brz %o2, 9f
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nop
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/* SUN4U TSB switch. */
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50: mov TSB_REG, %o5
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stxa %o0, [%o5] ASI_DMMU
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membar #Sync
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stxa %o0, [%o5] ASI_IMMU
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membar #Sync
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2: ldx [%o1 + TSB_CONFIG_MAP_VADDR], %o4
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brz %o4, 9f
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ldx [%o1 + TSB_CONFIG_MAP_PTE], %o5
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sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
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mov TLB_TAG_ACCESS, %g1
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mov TLB_TAG_ACCESS, %g3
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lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
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stxa %o2, [%g1] ASI_DMMU
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stxa %o4, [%g3] ASI_DMMU
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membar #Sync
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sllx %g2, 3, %g2
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stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS
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stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
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membar #Sync
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brz,pt %o2, 9f
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nop
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ldx [%o2 + TSB_CONFIG_MAP_VADDR], %o4
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ldx [%o2 + TSB_CONFIG_MAP_PTE], %o5
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mov TLB_TAG_ACCESS, %g3
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stxa %o4, [%g3] ASI_DMMU
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membar #Sync
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sub %g2, (1 << 3), %g2
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stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
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membar #Sync
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9:
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wrpr %o5, %pstate
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wrpr %g1, %pstate
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retl
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nop
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