Merge tag 'exynos-mcpm' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Exynos MCPM support for v3.16" from Kukjin Kim: - adding MCPM backend support for SMP secondary boot and core switching on Samsung's Exynos5420. Tested on exynos5420-smdk5420 and exynos5420 based chromebook (peach-pit) using the "/dev/b.L_switcher" user interface. Secondary core boot-up has also been tested on both the boards. * tag 'exynos-mcpm' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Add MCPM call-back functions ARM: dts: add CCI node for exynos5420 ARM: EXYNOS: Add generic cluster power control functions ARM: EXYNOS: use generic exynos cpu power control functions ARM: EXYNOS: Add generic cpu power control functions for exynos SoCs Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
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exynos5250-smdk5250.dtb \
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exynos5250-snow.dtb \
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exynos5420-arndale-octa.dtb \
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exynos5420-peach-pit.dtb \
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exynos5420-smdk5420.dtb \
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exynos5440-sd5v1.dtb \
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exynos5440-ssdk5440.dtb
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@@ -129,12 +129,10 @@
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <1>;
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clock-output-names = "cam_a_clkout", "cam_b_clkout";
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ranges;
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clock_cam: clock-controller {
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#clock-cells = <1>;
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};
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fimc_0: fimc@11800000 {
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compatible = "samsung,exynos4210-fimc";
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reg = <0x11800000 0x1000>;
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@@ -371,6 +369,8 @@
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interrupts = <0 60 0>;
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clocks = <&clock CLK_I2C2>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_bus>;
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status = "disabled";
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};
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@@ -382,6 +382,8 @@
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interrupts = <0 61 0>;
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clocks = <&clock CLK_I2C3>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_bus>;
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status = "disabled";
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};
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@@ -393,6 +395,8 @@
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interrupts = <0 62 0>;
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clocks = <&clock CLK_I2C4>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_bus>;
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status = "disabled";
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};
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@@ -404,6 +408,8 @@
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interrupts = <0 63 0>;
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clocks = <&clock CLK_I2C5>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_bus>;
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status = "disabled";
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};
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@@ -415,6 +421,8 @@
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interrupts = <0 64 0>;
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clocks = <&clock CLK_I2C6>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_bus>;
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status = "disabled";
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};
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@@ -426,6 +434,8 @@
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interrupts = <0 65 0>;
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clocks = <&clock CLK_I2C7>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_bus>;
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status = "disabled";
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};
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@@ -28,6 +28,21 @@
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bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
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};
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sysram@02020000 {
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smp-sysram@0 {
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status = "disabled";
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};
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smp-sysram@5000 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x5000 0x1000>;
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};
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smp-sysram@1f000 {
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status = "disabled";
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};
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};
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mct@10050000 {
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compatible = "none";
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};
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@@ -31,6 +31,24 @@
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pinctrl2 = &pinctrl_2;
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x20000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@1f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x1f000 0x1000>;
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};
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};
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pd_lcd1: lcd1-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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@@ -20,7 +20,7 @@
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compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
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aliases {
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i2c8 = &i2c_ak8975;
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i2c9 = &i2c_ak8975;
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};
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memory {
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@@ -80,7 +80,24 @@
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enable-active-high;
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};
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/* More to come */
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cam_af_reg: voltage-regulator-3 {
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compatible = "regulator-fixed";
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regulator-name = "CAM_AF";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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gpio = <&gpm0 4 0>;
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enable-active-high;
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};
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cam_isp_core_reg: voltage-regulator-4 {
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compatible = "regulator-fixed";
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regulator-name = "CAM_ISP_CORE_1.2V_EN";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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gpio = <&gpm0 3 0>;
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enable-active-high;
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regulator-always-on;
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};
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};
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gpio-keys {
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@@ -140,6 +157,38 @@
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};
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};
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i2c_0: i2c@13860000 {
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samsung,i2c-sda-delay = <100>;
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samsung,i2c-slave-addr = <0x10>;
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samsung,i2c-max-bus-freq = <400000>;
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pinctrl-0 = <&i2c0_bus>;
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pinctrl-names = "default";
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status = "okay";
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s5c73m3@3c {
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compatible = "samsung,s5c73m3";
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reg = <0x3c>;
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standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */
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xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */
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vdd-int-supply = <&buck9_reg>;
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vddio-cis-supply = <&ldo9_reg>;
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vdda-supply = <&ldo17_reg>;
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vddio-host-supply = <&ldo18_reg>;
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vdd-af-supply = <&cam_af_reg>;
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vdd-reg-supply = <&cam_io_reg>;
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clock-frequency = <24000000>;
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/* CAM_A_CLKOUT */
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clocks = <&camera 0>;
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clock-names = "cis_extclk";
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port {
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s5c73m3_ep: endpoint {
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remote-endpoint = <&csis0_ep>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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i2c@138D0000 {
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samsung,i2c-sda-delay = <100>;
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samsung,i2c-slave-addr = <0x10>;
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@@ -586,8 +635,8 @@
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status = "okay";
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};
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camera {
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pinctrl-0 = <&cam_port_b_clk_active>;
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camera: camera {
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pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
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pinctrl-names = "default";
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status = "okay";
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@@ -607,6 +656,23 @@
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status = "okay";
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};
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csis_0: csis@11880000 {
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status = "okay";
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vddcore-supply = <&ldo8_reg>;
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vddio-supply = <&ldo10_reg>;
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clock-frequency = <176000000>;
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/* Camera C (3) MIPI CSI-2 (CSIS0) */
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port@3 {
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reg = <3>;
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csis0_ep: endpoint {
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remote-endpoint = <&s5c73m3_ep>;
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data-lanes = <1 2 3 4>;
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samsung,csis-hs-settle = <12>;
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};
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};
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};
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csis_1: csis@11890000 {
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vddcore-supply = <&ldo8_reg>;
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vddio-supply = <&ldo10_reg>;
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@@ -647,10 +713,11 @@
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reg = <0x10>;
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svdda-supply = <&cam_io_reg>;
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svddio-supply = <&ldo19_reg>;
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afvdd-supply = <&ldo19_reg>;
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clock-frequency = <24000000>;
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/* CAM_B_CLKOUT */
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clocks = <&clock_cam 1>;
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clock-names = "mclk";
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clocks = <&camera 1>;
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clock-names = "extclk";
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samsung,camclk-out = <1>;
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gpios = <&gpm1 6 0>;
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@@ -37,6 +37,24 @@
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interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x40000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@2f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x2f000 0x1000>;
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};
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};
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pd_isp: isp-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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@@ -72,6 +72,24 @@
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};
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x30000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x30000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@2f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x2f000 0x1000>;
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};
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};
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pd_gsc: gsc-power-domain@10044000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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147
arch/arm/boot/dts/exynos5420-peach-pit.dts
Normal file
147
arch/arm/boot/dts/exynos5420-peach-pit.dts
Normal file
@@ -0,0 +1,147 @@
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/*
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* Google Peach Pit Rev 6+ board device tree source
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*
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* Copyright (c) 2014 Google, Inc
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "exynos5420.dtsi"
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/ {
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model = "Google Peach Pit Rev 6+";
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|
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compatible = "google,pit-rev16",
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"google,pit-rev15", "google,pit-rev14",
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"google,pit-rev13", "google,pit-rev12",
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"google,pit-rev11", "google,pit-rev10",
|
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"google,pit-rev9", "google,pit-rev8",
|
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"google,pit-rev7", "google,pit-rev6",
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"google,pit", "google,peach","samsung,exynos5420",
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"samsung,exynos5";
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|
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memory {
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reg = <0x20000000 0x80000000>;
|
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};
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fixed-rate-clocks {
|
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oscclk {
|
||||
compatible = "samsung,exynos5420-oscclk";
|
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clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&power_key_irq>;
|
||||
|
||||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm 0 1000000 0>;
|
||||
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
|
||||
default-brightness-level = <7>;
|
||||
pinctrl-0 = <&pwm0_out>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
tpm_irq: tpm-irq {
|
||||
samsung,pins = "gpx1-0";
|
||||
samsung,pin-function = <0>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
power_key_irq: power-key-irq {
|
||||
samsung,pins = "gpx1-2";
|
||||
samsung,pin-function = <0>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart_3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc_0 {
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
caps2-mmc-hs200-1_8v;
|
||||
supports-highspeed;
|
||||
non-removable;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <400000000>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <0 4>;
|
||||
samsung,dw-mshc-ddr-timing = <0 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc_2 {
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <400000000>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&hsi2c_9 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tpm@20 {
|
||||
compatible = "infineon,slb9645tt";
|
||||
reg = <0x20>;
|
||||
|
||||
/* Unused irq; but still need to configure the pins */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tpm_irq>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Use longest HW watchdog in SoC (32 seconds) since the hardware
|
||||
* watchdog provides no debugging information (compared to soft/hard
|
||||
* lockup detectors) and so should be last resort.
|
||||
*/
|
||||
&watchdog {
|
||||
timeout-sec = <32>;
|
||||
};
|
||||
@@ -624,6 +624,34 @@
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm0_out: pwm0-out {
|
||||
samsung,pins = "gpb2-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm1_out: pwm1-out {
|
||||
samsung,pins = "gpb2-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm2_out: pwm2-out {
|
||||
samsung,pins = "gpb2-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pwm3_out: pwm3-out {
|
||||
samsung,pins = "gpb2-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c7_hs_bus: i2c7-hs-bus {
|
||||
samsung,pins = "gpb2-2", "gpb2-3";
|
||||
samsung,pin-function = <3>;
|
||||
|
||||
@@ -58,6 +58,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@@ -65,6 +66,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
@@ -72,6 +74,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
@@ -79,6 +82,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
@@ -86,6 +90,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
@@ -93,6 +98,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
@@ -100,6 +106,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
@@ -107,6 +114,44 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci@10d20000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x10d20000 0x1000>;
|
||||
ranges = <0x0 0x10d20000 0x6000>;
|
||||
|
||||
cci_control0: slave-if@4000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
cci_control1: slave-if@5000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
sysram@02020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x02020000 0x54000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x02020000 0x54000>;
|
||||
|
||||
smp-sysram@0 {
|
||||
compatible = "samsung,exynos4210-sysram";
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
smp-sysram@53000 {
|
||||
compatible = "samsung,exynos4210-sysram-ns";
|
||||
reg = <0x53000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -125,7 +170,7 @@
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
mfc: codec@11000000 {
|
||||
compatible = "samsung,mfc-v7";
|
||||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
@@ -169,7 +214,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mct@101C0000 {
|
||||
mct: mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
@@ -270,7 +315,7 @@
|
||||
interrupts = <0 47 0>;
|
||||
};
|
||||
|
||||
rtc@101E0000 {
|
||||
rtc: rtc@101E0000 {
|
||||
clocks = <&clock CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
@@ -430,22 +475,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
uart_0: serial@12C00000 {
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
uart_1: serial@12C10000 {
|
||||
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
uart_2: serial@12C20000 {
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
uart_3: serial@12C30000 {
|
||||
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
@@ -465,14 +510,14 @@
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
dp-controller@145B0000 {
|
||||
dp: dp-controller@145B0000 {
|
||||
clocks = <&clock CLK_DP1>;
|
||||
clock-names = "dp";
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
};
|
||||
|
||||
fimd@14400000 {
|
||||
fimd: fimd@14400000 {
|
||||
samsung,power-domain = <&disp_pd>;
|
||||
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
@@ -632,7 +677,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi@14530000 {
|
||||
hdmi: hdmi@14530000 {
|
||||
compatible = "samsung,exynos4212-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
@@ -644,7 +689,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mixer@14450000 {
|
||||
mixer: mixer@14450000 {
|
||||
compatible = "samsung,exynos5420-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
@@ -715,7 +760,7 @@
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
watchdog@101D0000 {
|
||||
watchdog: watchdog@101D0000 {
|
||||
compatible = "samsung,exynos5420-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
@@ -724,7 +769,7 @@
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
};
|
||||
|
||||
sss@10830000 {
|
||||
sss: sss@10830000 {
|
||||
compatible = "samsung,exynos4210-secss";
|
||||
reg = <0x10830000 0x10000>;
|
||||
interrupts = <0 112 0>;
|
||||
|
||||
Reference in New Issue
Block a user