docs: arm: convert docs to ReST and rename to *.rst
Converts ARM the text files to ReST, preparing them to be an architecture book. The conversion is actually: - add blank lines and identation in order to identify paragraphs; - fix tables markups; - add some lists markups; - mark literal blocks; - adjust title markups. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Reviewed-by Corentin Labbe <clabbe.montjoie@gmail.com> # For sun4i-ss
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Mauro Carvalho Chehab
@@ -1,4 +1,6 @@
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MFP Configuration for PXA2xx/PXA3xx Processors
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==============================================
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MFP Configuration for PXA2xx/PXA3xx Processors
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==============================================
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Eric Miao <eric.miao@marvell.com>
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@@ -6,15 +8,15 @@ MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
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later PXA series processors. This document describes the existing MFP API,
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and how board/platform driver authors could make use of it.
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Basic Concept
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===============
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Basic Concept
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=============
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Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
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mechanism is introduced from PXA3xx to completely move the pin-mux functions
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out of the GPIO controller. In addition to pin-mux configurations, the MFP
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also controls the low power state, driving strength, pull-up/down and event
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detection of each pin. Below is a diagram of internal connections between
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the MFP logic and the remaining SoC peripherals:
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the MFP logic and the remaining SoC peripherals::
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+--------+
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| |--(GPIO19)--+
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@@ -69,8 +71,8 @@ NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
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mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
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pad (or ball).
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MFP API Usage
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===============
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MFP API Usage
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=============
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For board code writers, here are some guidelines:
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@@ -94,9 +96,9 @@ For board code writers, here are some guidelines:
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PXA310 supporting some additional ones), thus the difference is actually
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covered in a single mfp-pxa300.h.
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2. prepare an array for the initial pin configurations, e.g.:
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2. prepare an array for the initial pin configurations, e.g.::
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static unsigned long mainstone_pin_config[] __initdata = {
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static unsigned long mainstone_pin_config[] __initdata = {
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/* Chip Select */
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GPIO15_nCS_1,
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@@ -116,7 +118,7 @@ For board code writers, here are some guidelines:
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/* GPIO */
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GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
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};
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};
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a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
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and written to the actual registers, they are useless and may discard,
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@@ -143,17 +145,17 @@ For board code writers, here are some guidelines:
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d) although PXA3xx MFP supports edge detection on each pin, the
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internal logic will only wakeup the system when those specific bits
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in ADxER registers are set, which can be well mapped to the
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corresponding peripheral, thus set_irq_wake() can be called with
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corresponding peripheral, thus set_irq_wake() can be called with
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the peripheral IRQ to enable the wakeup.
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MFP on PXA3xx
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===============
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MFP on PXA3xx
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=============
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Every external I/O pad on PXA3xx (excluding those for special purpose) has
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one MFP logic associated, and is controlled by one MFP register (MFPR).
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The MFPR has the following bit definitions (for PXA300/PXA310/PXA320):
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The MFPR has the following bit definitions (for PXA300/PXA310/PXA320)::
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31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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+-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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@@ -183,8 +185,8 @@ The MFPR has the following bit definitions (for PXA300/PXA310/PXA320):
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0b006 - slow 10mA
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0b007 - fast 10mA
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MFP Design for PXA2xx/PXA3xx
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==============================
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MFP Design for PXA2xx/PXA3xx
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============================
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Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
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MFP API is introduced to cover both series of processors.
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@@ -194,11 +196,11 @@ configurations, these definitions are processor and platform independent, and
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the actual API invoked to convert these definitions into register settings and
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make them effective there-after.
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Files Involved
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--------------
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Files Involved
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--------------
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- arch/arm/mach-pxa/include/mach/mfp.h
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for
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1. Unified pin definitions - enum constants for all configurable pins
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2. processor-neutral bit definitions for a possible MFP configuration
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@@ -226,42 +228,42 @@ make them effective there-after.
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for implementation of the pin configuration to take effect for the actual
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processor.
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Pin Configuration
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-----------------
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Pin Configuration
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-----------------
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The following comments are copied from mfp.h (see the actual source code
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for most updated info)
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/*
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* a possible MFP configuration is represented by a 32-bit integer
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*
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* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
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* bit 10..12 - Alternate Function Selection
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* bit 13..15 - Drive Strength
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* bit 16..18 - Low Power Mode State
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* bit 19..20 - Low Power Mode Edge Detection
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* bit 21..22 - Run Mode Pull State
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*
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* to facilitate the definition, the following macros are provided
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*
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* MFP_CFG_DEFAULT - default MFP configuration value, with
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* alternate function = 0,
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* drive strength = fast 3mA (MFP_DS03X)
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* low power mode = default
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* edge detection = none
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*
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* MFP_CFG - default MFPR value with alternate function
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* MFP_CFG_DRV - default MFPR value with alternate function and
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* pin drive strength
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* MFP_CFG_LPM - default MFPR value with alternate function and
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* low power mode
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* MFP_CFG_X - default MFPR value with alternate function,
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* pin drive strength and low power mode
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*/
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for most updated info)::
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Examples of pin configurations are:
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/*
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* a possible MFP configuration is represented by a 32-bit integer
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*
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* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
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* bit 10..12 - Alternate Function Selection
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* bit 13..15 - Drive Strength
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* bit 16..18 - Low Power Mode State
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* bit 19..20 - Low Power Mode Edge Detection
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* bit 21..22 - Run Mode Pull State
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*
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* to facilitate the definition, the following macros are provided
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*
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* MFP_CFG_DEFAULT - default MFP configuration value, with
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* alternate function = 0,
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* drive strength = fast 3mA (MFP_DS03X)
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* low power mode = default
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* edge detection = none
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*
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* MFP_CFG - default MFPR value with alternate function
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* MFP_CFG_DRV - default MFPR value with alternate function and
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* pin drive strength
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* MFP_CFG_LPM - default MFPR value with alternate function and
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* low power mode
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* MFP_CFG_X - default MFPR value with alternate function,
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* pin drive strength and low power mode
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*/
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#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
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Examples of pin configurations are::
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#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
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which reads GPIO94 can be configured as SSP3_RXD, with alternate function
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selection of 1, driving strength of 0b101, and a float state in low power
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@@ -272,8 +274,8 @@ make them effective there-after.
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do so, simply because this default setting is usually carefully encoded,
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and is supposed to work in most cases.
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Register Settings
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-----------------
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Register Settings
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-----------------
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Register settings on PXA3xx for a pin configuration is actually very
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straight-forward, most bits can be converted directly into MFPR value
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