Merge tag 'davinci-for-v5.1/soc-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/late
DaVinci SoC updates for v5.1 (part 3) ------------------------------------- This pull request gets rid of mach-davinci private interrupt controller implmentations (aintc and cp_initc) and moves them to drivers/irqchip. mach/irqs.h usage outside of mach-davinci has been rid of. The driver changes (input and irqchip) have been acked by respective maintainers. * tag 'davinci-for-v5.1/soc-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (57 commits) ARM: davinci: remove intc related fields from davinci_soc_info irqchip: davinci-cp-intc: move the driver to drivers/irqchip ARM: davinci: cp-intc: remove redundant comments ARM: davinci: cp-intc: drop GPL license boilerplate ARM: davinci: cp-intc: use readl/writel_relaxed() ARM: davinci: cp-intc: unify error handling ARM: davinci: cp-intc: improve coding style ARM: davinci: cp-intc: request the memory region before remapping it ARM: davinci: cp-intc: use the new-style config structure ARM: davinci: cp-intc: convert all hex numbers to lowercase ARM: davinci: cp-intc: use a common prefix for all symbols ARM: davinci: cp-intc: add the new config structures for da8xx SoCs irqchip: davinci-cp-intc: add a new config structure ARM: davinci: cp-intc: add a wrapper around cp_intc_init() ARM: davinci: cp-intc: remove cp_intc.h irqchip: davinci-aintc: move the driver to drivers/irqchip ARM: davinci: aintc: remove unnecessary includes ARM: davinci: aintc: remove the timer-specific irq_set_handler() ARM: davinci: aintc: request memory region before remapping it ARM: davinci: aintc: unify error handling ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -129,6 +129,16 @@ config BRCMSTB_L2_IRQ
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_AINTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_CP_INTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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@@ -6,6 +6,8 @@ obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
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obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
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obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
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163
drivers/irqchip/irq-davinci-aintc.c
Normal file
163
drivers/irqchip/irq-davinci-aintc.c
Normal file
@@ -0,0 +1,163 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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//
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// Copyright (C) 2006, 2019 Texas Instruments.
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//
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// Interrupt handler for DaVinci boards.
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/irq-davinci-aintc.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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#define DAVINCI_AINTC_FIQ_REG0 0x00
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#define DAVINCI_AINTC_FIQ_REG1 0x04
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#define DAVINCI_AINTC_IRQ_REG0 0x08
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#define DAVINCI_AINTC_IRQ_REG1 0x0c
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#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
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#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
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#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
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#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
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#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
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#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
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#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
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static void __iomem *davinci_aintc_base;
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static struct irq_domain *davinci_aintc_irq_domain;
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static inline void davinci_aintc_writel(unsigned long value, int offset)
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{
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writel_relaxed(value, davinci_aintc_base + offset);
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}
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static inline unsigned long davinci_aintc_readl(int offset)
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{
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return readl_relaxed(davinci_aintc_base + offset);
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}
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static __init void
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davinci_aintc_setup_gc(void __iomem *base,
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unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
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gc->reg_base = base;
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gc->irq_base = irq_start;
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
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ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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static asmlinkage void __exception_irq_entry
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davinci_aintc_handle_irq(struct pt_regs *regs)
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{
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int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
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/*
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* Use the formula for entry vector index generation from section
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* 8.3.3 of the manual.
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*/
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irqnr >>= 2;
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irqnr -= 1;
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handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs);
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}
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/* ARM Interrupt Controller Initialization */
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void __init davinci_aintc_init(const struct davinci_aintc_config *config)
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{
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unsigned int irq_off, reg_off, prio, shift;
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void __iomem *req;
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int ret, irq_base;
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const u8 *prios;
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req = request_mem_region(config->reg.start,
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resource_size(&config->reg),
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"davinci-cp-intc");
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if (!req) {
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pr_err("%s: register range busy\n", __func__);
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return;
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}
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davinci_aintc_base = ioremap(config->reg.start,
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resource_size(&config->reg));
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if (!davinci_aintc_base) {
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pr_err("%s: unable to ioremap register range\n", __func__);
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return;
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}
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/* Clear all interrupt requests */
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
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/* Disable all interrupts */
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davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
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davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
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/* Interrupts disabled immediately, IRQ entry reflects all */
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davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
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/* we don't use the hardware vector table, just its entry addresses */
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davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
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/* Clear all interrupt requests */
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
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prios = config->prios;
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for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG;
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reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) {
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for (shift = 0, prio = 0; shift < 32; shift += 4, prios++)
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prio |= (*prios & 0x07) << shift;
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davinci_aintc_writel(prio, reg_off);
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}
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irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
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if (irq_base < 0) {
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pr_err("%s: unable to allocate interrupt descriptors: %d\n",
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__func__, irq_base);
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return;
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}
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davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
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config->num_irqs, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!davinci_aintc_irq_domain) {
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pr_err("%s: unable to create interrupt domain\n", __func__);
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return;
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}
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ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
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"AINTC", handle_edge_irq,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
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if (ret) {
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pr_err("%s: unable to allocate generic irq chips for domain\n",
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__func__);
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return;
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}
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for (irq_off = 0, reg_off = 0;
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irq_off < config->num_irqs;
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irq_off += 32, reg_off += 0x04)
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davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
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irq_base + irq_off, 32);
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set_handle_irq(davinci_aintc_handle_irq);
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}
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260
drivers/irqchip/irq-davinci-cp-intc.c
Normal file
260
drivers/irqchip/irq-davinci-cp-intc.c
Normal file
@@ -0,0 +1,260 @@
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// Author: Steve Chen <schen@mvista.com>
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// Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
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// Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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// Copyright (C) 2019, Texas Instruments
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//
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// TI Common Platform Interrupt Controller (cp_intc) driver
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/irq-davinci-cp-intc.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#define DAVINCI_CP_INTC_CTRL 0x04
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#define DAVINCI_CP_INTC_HOST_CTRL 0x0c
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#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
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#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
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#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
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#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
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#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
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#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
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#define DAVINCI_CP_INTC_PRIO_IDX 0x80
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#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
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#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
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#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
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#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0d00 + (n << 2))
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#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0d80 + (n << 2))
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#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
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#define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)
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#define DAVINCI_CP_INTC_GPIR_NONE BIT(31)
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static void __iomem *davinci_cp_intc_base;
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static struct irq_domain *davinci_cp_intc_irq_domain;
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static inline unsigned int davinci_cp_intc_read(unsigned int offset)
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{
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return readl_relaxed(davinci_cp_intc_base + offset);
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}
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static inline void davinci_cp_intc_write(unsigned long value,
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unsigned int offset)
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{
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writel_relaxed(value, davinci_cp_intc_base + offset);
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}
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static void davinci_cp_intc_ack_irq(struct irq_data *d)
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{
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davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
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}
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static void davinci_cp_intc_mask_irq(struct irq_data *d)
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{
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/* XXX don't know why we need to disable nIRQ here... */
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davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
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davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
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davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
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}
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static void davinci_cp_intc_unmask_irq(struct irq_data *d)
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{
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davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
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}
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static int davinci_cp_intc_set_irq_type(struct irq_data *d,
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unsigned int flow_type)
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{
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unsigned int reg, mask, polarity, type;
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reg = BIT_WORD(d->hwirq);
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mask = BIT_MASK(d->hwirq);
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polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
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type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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polarity |= mask;
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type |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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polarity &= ~mask;
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type |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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polarity |= mask;
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type &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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polarity &= ~mask;
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type &= ~mask;
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break;
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default:
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return -EINVAL;
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}
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davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
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davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
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return 0;
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}
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static struct irq_chip davinci_cp_intc_irq_chip = {
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.name = "cp_intc",
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.irq_ack = davinci_cp_intc_ack_irq,
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.irq_mask = davinci_cp_intc_mask_irq,
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.irq_unmask = davinci_cp_intc_unmask_irq,
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.irq_set_type = davinci_cp_intc_set_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
|
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static asmlinkage void __exception_irq_entry
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davinci_cp_intc_handle_irq(struct pt_regs *regs)
|
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{
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int gpir, irqnr, none;
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/*
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* The interrupt number is in first ten bits. The NONE field set to 1
|
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* indicates a spurious irq.
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*/
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gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
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irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
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none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
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if (unlikely(none)) {
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pr_err_once("%s: spurious irq!\n", __func__);
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return;
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}
|
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handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs);
|
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}
|
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static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
|
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{
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pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
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irq_set_chip(virq, &davinci_cp_intc_irq_chip);
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irq_set_probe(virq);
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irq_set_handler(virq, handle_edge_irq);
|
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|
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return 0;
|
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}
|
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|
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static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
|
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.map = davinci_cp_intc_host_map,
|
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.xlate = irq_domain_xlate_onetwocell,
|
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};
|
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|
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static int __init
|
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davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
|
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struct device_node *node)
|
||||
{
|
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unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
|
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int offset, irq_base;
|
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void __iomem *req;
|
||||
|
||||
req = request_mem_region(config->reg.start,
|
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resource_size(&config->reg),
|
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"davinci-cp-intc");
|
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if (!req) {
|
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pr_err("%s: register range busy\n", __func__);
|
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return -EBUSY;
|
||||
}
|
||||
|
||||
davinci_cp_intc_base = ioremap(config->reg.start,
|
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resource_size(&config->reg));
|
||||
if (!davinci_cp_intc_base) {
|
||||
pr_err("%s: unable to ioremap register range\n", __func__);
|
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return -EINVAL;
|
||||
}
|
||||
|
||||
davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
|
||||
|
||||
/* Disable all host interrupts */
|
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davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
|
||||
|
||||
/* Disable system interrupts */
|
||||
for (offset = 0; offset < num_regs; offset++)
|
||||
davinci_cp_intc_write(~0,
|
||||
DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
|
||||
|
||||
/* Set to normal mode, no nesting, no priority hold */
|
||||
davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
|
||||
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
|
||||
|
||||
/* Clear system interrupt status */
|
||||
for (offset = 0; offset < num_regs; offset++)
|
||||
davinci_cp_intc_write(~0,
|
||||
DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
|
||||
|
||||
/* Enable nIRQ (what about nFIQ?) */
|
||||
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
|
||||
|
||||
/* Default all priorities to channel 7. */
|
||||
num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
|
||||
for (offset = 0; offset < num_regs; offset++)
|
||||
davinci_cp_intc_write(0x07070707,
|
||||
DAVINCI_CP_INTC_CHAN_MAP(offset));
|
||||
|
||||
irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
|
||||
if (irq_base < 0) {
|
||||
pr_err("%s: unable to allocate interrupt descriptors: %d\n",
|
||||
__func__, irq_base);
|
||||
return irq_base;
|
||||
}
|
||||
|
||||
davinci_cp_intc_irq_domain = irq_domain_add_legacy(
|
||||
node, config->num_irqs, irq_base, 0,
|
||||
&davinci_cp_intc_irq_domain_ops, NULL);
|
||||
|
||||
if (!davinci_cp_intc_irq_domain) {
|
||||
pr_err("%s: unable to create an interrupt domain\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
set_handle_irq(davinci_cp_intc_handle_irq);
|
||||
|
||||
/* Enable global interrupt */
|
||||
davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
|
||||
{
|
||||
return davinci_cp_intc_do_init(config, NULL);
|
||||
}
|
||||
|
||||
static int __init davinci_cp_intc_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct davinci_cp_intc_config config = { };
|
||||
int ret;
|
||||
|
||||
ret = of_address_to_resource(node, 0, &config.reg);
|
||||
if (ret) {
|
||||
pr_err("%s: unable to get the register range from device-tree\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
|
||||
if (ret) {
|
||||
pr_err("%s: unable to read the 'ti,intc-size' property\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return davinci_cp_intc_do_init(&config, node);
|
||||
}
|
||||
IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);
|
||||
Reference in New Issue
Block a user