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drm/amdgpu: Fix the exported always on CU bitmap

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Newer asics with 4 SEs are not able to fit the entire bitmask in the
original field, use an array instead.

v2: keep cu_ao_mask for backward compatibility.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Flora Cui
2017-06-20 11:08:35 +08:00
committed by Alex Deucher
parent 552c8f76af
commit dbfe85ea49
8 changed files with 24 additions and 7 deletions
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7
drivers/gpu/drm/amd/amdgpu/amdgpu.h
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@@ -1028,12 +1028,15 @@ struct amdgpu_gfx_config {
}; };
struct amdgpu_cu_info { struct amdgpu_cu_info {
uint32_t number; /* total active CU number */
uint32_t ao_cu_mask;
uint32_t max_waves_per_simd; uint32_t max_waves_per_simd;
uint32_t wave_front_size; uint32_t wave_front_size;
uint32_t max_scratch_slots_per_cu; uint32_t max_scratch_slots_per_cu;
uint32_t lds_size; uint32_t lds_size;
/* total active CU number */
uint32_t number;
uint32_t ao_cu_mask;
uint32_t ao_cu_bitmap[4][4];
uint32_t bitmap[4][4]; uint32_t bitmap[4][4];
}; };

3
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
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@@ -67,9 +67,10 @@
* - 3.15.0 - Export more gpu info for gfx9 * - 3.15.0 - Export more gpu info for gfx9
* - 3.16.0 - Add reserved vmid support * - 3.16.0 - Add reserved vmid support
* - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
* - 3.18.0 - Export gpu always on cu bitmap
*/ */
#define KMS_DRIVER_MAJOR 3 #define KMS_DRIVER_MAJOR 3
#define KMS_DRIVER_MINOR 17 #define KMS_DRIVER_MINOR 18
#define KMS_DRIVER_PATCHLEVEL 0 #define KMS_DRIVER_PATCHLEVEL 0
int amdgpu_vram_limit = 0; int amdgpu_vram_limit = 0;

2
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@@ -594,6 +594,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
dev_info.cu_active_number = adev->gfx.cu_info.number; dev_info.cu_active_number = adev->gfx.cu_info.number;
dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
dev_info.ce_ram_size = adev->gfx.ce_ram_size; dev_info.ce_ram_size = adev->gfx.ce_ram_size;
memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
sizeof(adev->gfx.cu_info.ao_cu_bitmap));
memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
sizeof(adev->gfx.cu_info.bitmap)); sizeof(adev->gfx.cu_info.bitmap));
dev_info.vram_type = adev->mc.vram_type; dev_info.vram_type = adev->mc.vram_type;

4
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
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@@ -3535,7 +3535,9 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
mask <<= 1; mask <<= 1;
} }
active_cu_number += counter; active_cu_number += counter;
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); if (i < 2 && j < 2)
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
} }
} }

4
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@@ -5427,7 +5427,9 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
mask <<= 1; mask <<= 1;
} }
active_cu_number += counter; active_cu_number += counter;
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); if (i < 2 && j < 2)
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
} }
} }
gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

4
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@@ -7087,7 +7087,9 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
mask <<= 1; mask <<= 1;
} }
active_cu_number += counter; active_cu_number += counter;
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); if (i < 2 && j < 2)
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
} }
} }
gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@@ -4459,7 +4459,9 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
mask <<= 1; mask <<= 1;
} }
active_cu_number += counter; active_cu_number += counter;
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); if (i < 2 && j < 2)
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
} }
} }
gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

3
include/uapi/drm/amdgpu_drm.h
View File

@@ -764,6 +764,7 @@ struct drm_amdgpu_info_device {
__u64 max_memory_clock; __u64 max_memory_clock;
/* cu information */ /* cu information */
__u32 cu_active_number; __u32 cu_active_number;
/* NOTE: cu_ao_mask is INVALID, DON'T use it */
__u32 cu_ao_mask; __u32 cu_ao_mask;
__u32 cu_bitmap[4][4]; __u32 cu_bitmap[4][4];
/** Render backend pipe mask. One render backend is CB+DB. */ /** Render backend pipe mask. One render backend is CB+DB. */
@@ -818,6 +819,8 @@ struct drm_amdgpu_info_device {
/* max gs wavefront per vgt*/ /* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt; __u32 max_gs_waves_per_vgt;
__u32 _pad1; __u32 _pad1;
/* always on cu bitmap */
__u32 cu_ao_bitmap[4][4];
}; };
struct drm_amdgpu_info_hw_ip { struct drm_amdgpu_info_hw_ip {