drm/i915: add frontbuffer tracking to FBC
Kill the blt/render tracking we currently have and use the frontbuffer tracking infrastructure. Don't enable things by default yet. v2: (Rodrigo) Fix small conflict on rebase and typo at subject. v3: (Paulo) Rebase on RENDER_CS change. v4: (Paulo) Rebase. v5: (Paulo) Simplify: flushes don't have origin (Daniel). Also rebase due to patch order changes. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter

parent
3954e733ab
commit
dbef0f15b5
@@ -118,8 +118,6 @@ static void intel_mark_fb_busy(struct drm_device *dev,
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continue;
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intel_increase_pllclock(dev, pipe);
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if (ring && intel_fbc_enabled(dev))
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ring->fbc_dirty = true;
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}
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}
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@@ -160,6 +158,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
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intel_psr_invalidate(dev, obj->frontbuffer_bits);
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intel_edp_drrs_invalidate(dev, obj->frontbuffer_bits);
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intel_fbc_invalidate(dev_priv, obj->frontbuffer_bits, origin);
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}
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/**
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@@ -187,16 +186,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
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intel_edp_drrs_flush(dev, frontbuffer_bits);
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intel_psr_flush(dev, frontbuffer_bits);
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/*
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* FIXME: Unconditional fbc flushing here is a rather gross hack and
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* needs to be reworked into a proper frontbuffer tracking scheme like
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* psr employs.
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*/
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if (dev_priv->fbc.need_sw_cache_clean) {
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dev_priv->fbc.need_sw_cache_clean = false;
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bdw_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
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}
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intel_fbc_flush(dev_priv, frontbuffer_bits);
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}
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/**
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