net: dsa: qca8k: extend slave-bus implementations
This patch implements accessors for the QCA8337 MDIO access through the MDIO_MASTER register, which makes it possible to access the PHYs on slave-bus through the switch. In cases where the switch ports are already mapped via external "phy-phandles", the internal mdio-bus is disabled in order to prevent a duplicated discovery and enumeration of the same PHYs. Don't use mixed external and internal mdio-bus configurations, as this is not supported by the hardware. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller

parent
1eec7151ae
commit
db460c54b6
@@ -49,6 +49,18 @@
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#define QCA8K_MIB_FLUSH BIT(24)
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#define QCA8K_MIB_CPU_KEEP BIT(20)
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#define QCA8K_MIB_BUSY BIT(17)
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#define QCA8K_MDIO_MASTER_CTRL 0x3c
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#define QCA8K_MDIO_MASTER_BUSY BIT(31)
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#define QCA8K_MDIO_MASTER_EN BIT(30)
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#define QCA8K_MDIO_MASTER_READ BIT(27)
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#define QCA8K_MDIO_MASTER_WRITE 0
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#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
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#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
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#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
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#define QCA8K_MDIO_MASTER_DATA(x) (x)
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#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
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#define QCA8K_MDIO_MASTER_MAX_PORTS 5
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#define QCA8K_MDIO_MASTER_MAX_REG 32
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#define QCA8K_GOL_MAC_ADDR0 0x60
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#define QCA8K_GOL_MAC_ADDR1 0x64
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#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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@@ -169,6 +181,7 @@ struct qca8k_priv {
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struct dsa_switch *ds;
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struct mutex reg_mutex;
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struct device *dev;
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struct dsa_switch_ops ops;
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};
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struct qca8k_mib_desc {
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