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Merge tag 'mips_fixes_4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

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Pull MIPS fixes from James Hogan:
 "A selection of important MIPS fixes for 4.14, and some MAINTAINERS /
  email address updates:

  Maintainership updates:
   - imgtec.com -> mips.com email addresses (this trivially updates
     comments in quite a few files, as well as MAINTAINERS)
   - Pistachio SoC maintainership update

  Fixes:
   - NI 169445 build (new platform in 4.14)
   - EVA regression (4.14)
   - SMP-CPS build & preemption regressions (4.14)
   - SMP/hotplug deadlock & race (deadlock reintroduced 4.13)
   - ebpf_jit error return (4.13)
   - SMP-CMP build regressions (4.11 and 4.14)
   - bad UASM microMIPS encoding (3.16)
   - CM definitions (3.15)"

[ I had taken the email address updates separately, because I didn't
  expect James to send a pull request, so those got applied twice.   - Linus]

* tag 'mips_fixes_4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips:
  MIPS: Update email address for Marcin Nowakowski
  MIPS: smp-cmp: Fix vpe_id build error
  MAINTAINERS: Update Pistachio platform maintainers
  MIPS: smp-cmp: Use right include for task_struct
  MIPS: Update Goldfish RTC driver maintainer email address
  MIPS: Update RINT emulation maintainer email address
  MIPS: CPS: Fix use of current_cpu_data in preemptible code
  MIPS: SMP: Fix deadlock & online race
  MIPS: bpf: Fix a typo in build_one_insn()
  MIPS: microMIPS: Fix incorrect mask in insn_table_MM
  MIPS: Fix CM region target definitions
  MIPS: generic: Fix compilation error from include asm/mips-cpc.h
  MIPS: Fix exception entry when CONFIG_EVA enabled
  MIPS: generic: Fix NI 169445 its build
  Update MIPS email addresses
This commit is contained in:
Linus Torvalds
2017-11-04 11:31:02 -07:00
parent e50f82f809 ca208b5f19
commit dab30d5531
13 changed files with 40 additions and 28 deletions
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2
arch/mips/mm/uasm-micromips.c
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@@ -80,7 +80,7 @@ static const struct insn const insn_table_MM[insn_invalid] = {
[insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
[insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
[insn_ld] = {0, 0},
[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM},
[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
[insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
[insn_lld] = {0, 0},
[insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},