drm/amd/powerplay: add the hw manager for vega20 (v3)
hwmgr is the interface for the driver to setup state structures which are used by the smu for managing the power state. v2: squash in fixes: - update set_watermarks_for_clocks_ranges to use common code - drop unsupported apis - correct MAX_REGULAR_DPM_NUMBER value - multimonitor fixes - add check for vbios pptable version - revise dpm table setup - init fclk dpm state - Remove unused definition in vega20_hwmgr - support power limit setup - enable vega20 to honour DAL clock limits - comment out dump_table debugging v3: switch to SOC15 register access macros Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
@@ -33,7 +33,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
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vega10_thermal.o smu10_hwmgr.o pp_psm.o\
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vega12_processpptables.o vega12_hwmgr.o \
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vega12_thermal.o \
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pp_overdriver.o smu_helper.o
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pp_overdriver.o smu_helper.o \
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vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
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vega20_thermal.o
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AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
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@@ -44,11 +44,13 @@ extern const struct pp_smumgr_func vegam_smu_funcs;
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extern const struct pp_smumgr_func vega10_smu_funcs;
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extern const struct pp_smumgr_func vega12_smu_funcs;
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extern const struct pp_smumgr_func smu10_smu_funcs;
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extern const struct pp_smumgr_func vega20_smu_funcs;
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extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
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extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
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extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
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static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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@@ -149,7 +151,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
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case AMDGPU_FAMILY_AI:
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switch (hwmgr->chip_id) {
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case CHIP_VEGA10:
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case CHIP_VEGA20:
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hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
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hwmgr->smumgr_funcs = &vega10_smu_funcs;
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vega10_hwmgr_init(hwmgr);
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@@ -158,6 +159,11 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
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hwmgr->smumgr_funcs = &vega12_smu_funcs;
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vega12_hwmgr_init(hwmgr);
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break;
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case CHIP_VEGA20:
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hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
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hwmgr->smumgr_funcs = &vega20_smu_funcs;
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vega20_hwmgr_init(hwmgr);
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break;
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default:
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return -EINVAL;
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}
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2099
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
Normal file
2099
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
Normal file
A különbségek nem kerülnek megjelenítésre, mivel a fájl túl nagy
Load Diff
519
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
Normal file
519
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
Normal file
@@ -0,0 +1,519 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _VEGA20_HWMGR_H_
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#define _VEGA20_HWMGR_H_
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#include "hwmgr.h"
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#include "smu11_driver_if.h"
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#include "ppatomfwctrl.h"
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#define VEGA20_MAX_HARDWARE_POWERLEVELS 2
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#define WaterMarksExist 1
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#define WaterMarksLoaded 2
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#define VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS 8
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#define VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8
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#define VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8
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#define VG20_PSUEDO_NUM_UCLK_DPM_LEVELS 4
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typedef uint32_t PP_Clock;
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enum {
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GNLD_DPM_PREFETCHER = 0,
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GNLD_DPM_GFXCLK,
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GNLD_DPM_UCLK,
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GNLD_DPM_SOCCLK,
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GNLD_DPM_UVD,
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GNLD_DPM_VCE,
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GNLD_ULV,
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GNLD_DPM_MP0CLK,
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GNLD_DPM_LINK,
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GNLD_DPM_DCEFCLK,
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GNLD_DS_GFXCLK,
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GNLD_DS_SOCCLK,
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GNLD_DS_LCLK,
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GNLD_PPT,
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GNLD_TDC,
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GNLD_THERMAL,
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GNLD_GFX_PER_CU_CG,
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GNLD_RM,
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GNLD_DS_DCEFCLK,
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GNLD_ACDC,
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GNLD_VR0HOT,
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GNLD_VR1HOT,
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GNLD_FW_CTF,
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GNLD_LED_DISPLAY,
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GNLD_FAN_CONTROL,
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GNLD_DIDT,
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GNLD_GFXOFF,
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GNLD_CG,
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GNLD_DPM_FCLK,
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GNLD_DS_FCLK,
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GNLD_DS_MP1CLK,
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GNLD_DS_MP0CLK,
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GNLD_XGMI,
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GNLD_FEATURES_MAX
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};
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#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1)
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#define SMC_DPM_FEATURES 0x30F
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struct smu_features {
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bool supported;
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bool enabled;
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bool allowed;
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uint32_t smu_feature_id;
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uint64_t smu_feature_bitmap;
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};
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struct vega20_performance_level {
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uint32_t soc_clock;
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uint32_t gfx_clock;
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uint32_t mem_clock;
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};
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struct vega20_bacos {
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uint32_t baco_flags;
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/* struct vega20_performance_level performance_level; */
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};
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struct vega20_uvd_clocks {
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uint32_t vclk;
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uint32_t dclk;
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};
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struct vega20_vce_clocks {
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uint32_t evclk;
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uint32_t ecclk;
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};
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struct vega20_power_state {
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uint32_t magic;
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struct vega20_uvd_clocks uvd_clks;
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struct vega20_vce_clocks vce_clks;
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uint16_t performance_level_count;
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bool dc_compatible;
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uint32_t sclk_threshold;
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struct vega20_performance_level performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS];
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};
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struct vega20_dpm_level {
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bool enabled;
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uint32_t value;
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uint32_t param1;
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};
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#define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define MAX_REGULAR_DPM_NUMBER 16
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#define MAX_PCIE_CONF 2
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#define VEGA20_MINIMUM_ENGINE_CLOCK 2500
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struct vega20_max_sustainable_clocks {
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PP_Clock display_clock;
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PP_Clock phy_clock;
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PP_Clock pixel_clock;
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PP_Clock uclock;
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PP_Clock dcef_clock;
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PP_Clock soc_clock;
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};
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struct vega20_dpm_state {
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uint32_t soft_min_level;
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uint32_t soft_max_level;
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uint32_t hard_min_level;
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uint32_t hard_max_level;
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};
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struct vega20_single_dpm_table {
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uint32_t count;
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struct vega20_dpm_state dpm_state;
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struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega20_odn_dpm_control {
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uint32_t count;
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uint32_t entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega20_pcie_table {
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uint16_t count;
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uint8_t pcie_gen[MAX_PCIE_CONF];
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uint8_t pcie_lane[MAX_PCIE_CONF];
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uint32_t lclk[MAX_PCIE_CONF];
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};
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struct vega20_dpm_table {
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struct vega20_single_dpm_table soc_table;
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struct vega20_single_dpm_table gfx_table;
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struct vega20_single_dpm_table mem_table;
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struct vega20_single_dpm_table eclk_table;
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struct vega20_single_dpm_table vclk_table;
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struct vega20_single_dpm_table dclk_table;
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struct vega20_single_dpm_table dcef_table;
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struct vega20_single_dpm_table pixel_table;
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struct vega20_single_dpm_table display_table;
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struct vega20_single_dpm_table phy_table;
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struct vega20_single_dpm_table fclk_table;
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struct vega20_pcie_table pcie_table;
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};
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#define VEGA20_MAX_LEAKAGE_COUNT 8
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struct vega20_leakage_voltage {
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uint16_t count;
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uint16_t leakage_id[VEGA20_MAX_LEAKAGE_COUNT];
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uint16_t actual_voltage[VEGA20_MAX_LEAKAGE_COUNT];
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};
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struct vega20_display_timing {
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uint32_t min_clock_in_sr;
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uint32_t num_existing_displays;
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};
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struct vega20_dpmlevel_enable_mask {
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uint32_t uvd_dpm_enable_mask;
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uint32_t vce_dpm_enable_mask;
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uint32_t samu_dpm_enable_mask;
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uint32_t sclk_dpm_enable_mask;
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uint32_t mclk_dpm_enable_mask;
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};
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struct vega20_vbios_boot_state {
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bool bsoc_vddc_lock;
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uint8_t uc_cooling_id;
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uint16_t vddc;
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uint16_t vddci;
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uint16_t mvddc;
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uint16_t vdd_gfx;
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uint32_t gfx_clock;
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uint32_t mem_clock;
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uint32_t soc_clock;
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uint32_t dcef_clock;
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uint32_t eclock;
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uint32_t dclock;
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uint32_t vclock;
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
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#define DPMTABLE_OD_UPDATE_SCLK_MASK 0x00000020
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#define DPMTABLE_OD_UPDATE_MCLK_MASK 0x00000040
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// To determine if sclk and mclk are in overdrive state
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#define SCLK_MASK_OVERDRIVE_ENABLED 0x00000008
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#define MCLK_MASK_OVERDRIVE_ENABLED 0x00000010
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#define SOCCLK_OVERDRIVE_ENABLED 0x00000020
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struct vega20_smc_state_table {
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uint32_t soc_boot_level;
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uint32_t gfx_boot_level;
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uint32_t dcef_boot_level;
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uint32_t mem_boot_level;
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uint32_t uvd_boot_level;
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uint32_t vce_boot_level;
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uint32_t gfx_max_level;
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uint32_t mem_max_level;
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uint8_t vr_hot_gpio;
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uint8_t ac_dc_gpio;
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uint8_t therm_out_gpio;
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uint8_t therm_out_polarity;
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uint8_t therm_out_mode;
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PPTable_t pp_table;
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Watermarks_t water_marks_table;
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AvfsDebugTable_t avfs_debug_table;
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AvfsFuseOverride_t avfs_fuse_override_table;
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SmuMetrics_t smu_metrics;
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DriverSmuConfig_t driver_smu_config;
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DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
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OverDriveTable_t overdrive_table;
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};
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struct vega20_mclk_latency_entries {
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uint32_t frequency;
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uint32_t latency;
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};
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struct vega20_mclk_latency_table {
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uint32_t count;
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struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega20_registry_data {
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uint64_t disallowed_features;
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uint8_t ac_dc_switch_gpio_support;
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uint8_t acg_loop_support;
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uint8_t clock_stretcher_support;
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uint8_t db_ramping_support;
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uint8_t didt_mode;
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uint8_t didt_support;
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uint8_t edc_didt_support;
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uint8_t force_dpm_high;
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uint8_t fuzzy_fan_control_support;
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uint8_t mclk_dpm_key_disabled;
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uint8_t od_state_in_dc_support;
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uint8_t pcie_lane_override;
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uint8_t pcie_speed_override;
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uint32_t pcie_clock_override;
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uint8_t pcie_dpm_key_disabled;
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uint8_t dcefclk_dpm_key_disabled;
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uint8_t prefetcher_dpm_key_disabled;
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uint8_t quick_transition_support;
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uint8_t regulator_hot_gpio_support;
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uint8_t master_deep_sleep_support;
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uint8_t gfx_clk_deep_sleep_support;
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uint8_t sclk_deep_sleep_support;
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uint8_t lclk_deep_sleep_support;
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uint8_t dce_fclk_deep_sleep_support;
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uint8_t sclk_dpm_key_disabled;
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uint8_t sclk_throttle_low_notification;
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uint8_t skip_baco_hardware;
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uint8_t socclk_dpm_key_disabled;
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uint8_t sq_ramping_support;
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uint8_t tcp_ramping_support;
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uint8_t td_ramping_support;
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uint8_t dbr_ramping_support;
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uint8_t gc_didt_support;
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uint8_t psm_didt_support;
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uint8_t thermal_support;
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uint8_t fw_ctf_enabled;
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uint8_t led_dpm_enabled;
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uint8_t fan_control_support;
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uint8_t ulv_support;
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uint8_t odn_feature_enable;
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uint8_t disable_water_mark;
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uint8_t disable_workload_policy;
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uint32_t force_workload_policy_mask;
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uint8_t disable_3d_fs_detection;
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uint8_t disable_pp_tuning;
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uint8_t disable_xlpp_tuning;
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uint32_t perf_ui_tuning_profile_turbo;
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uint32_t perf_ui_tuning_profile_powerSave;
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uint32_t perf_ui_tuning_profile_xl;
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uint16_t zrpm_stop_temp;
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uint16_t zrpm_start_temp;
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uint32_t stable_pstate_sclk_dpm_percentage;
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uint8_t fps_support;
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uint8_t vr0hot;
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uint8_t vr1hot;
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uint8_t disable_auto_wattman;
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uint32_t auto_wattman_debug;
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uint32_t auto_wattman_sample_period;
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uint8_t auto_wattman_threshold;
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uint8_t log_avfs_param;
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uint8_t enable_enginess;
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uint8_t custom_fan_support;
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uint8_t disable_pcc_limit_control;
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uint8_t gfxoff_controlled_by_driver;
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};
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struct vega20_odn_clock_voltage_dependency_table {
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uint32_t count;
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struct phm_ppt_v1_clock_voltage_dependency_record
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entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega20_odn_dpm_table {
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struct vega20_odn_dpm_control control_gfxclk_state;
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struct vega20_odn_dpm_control control_memclk_state;
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struct phm_odn_clock_levels odn_core_clock_dpm_levels;
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struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
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struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
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struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
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struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_socclk;
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uint32_t odn_mclk_min_limit;
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};
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struct vega20_odn_fan_table {
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uint32_t target_fan_speed;
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uint32_t target_temperature;
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uint32_t min_performance_clock;
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uint32_t min_fan_limit;
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bool force_fan_pwm;
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};
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||||
struct vega20_odn_temp_table {
|
||||
uint16_t target_operating_temp;
|
||||
uint16_t default_target_operating_temp;
|
||||
uint16_t operating_temp_min_limit;
|
||||
uint16_t operating_temp_max_limit;
|
||||
uint16_t operating_temp_step;
|
||||
};
|
||||
|
||||
struct vega20_odn_data {
|
||||
uint32_t apply_overdrive_next_settings_mask;
|
||||
uint32_t overdrive_next_state;
|
||||
uint32_t overdrive_next_capabilities;
|
||||
uint32_t odn_sclk_dpm_enable_mask;
|
||||
uint32_t odn_mclk_dpm_enable_mask;
|
||||
struct vega20_odn_dpm_table odn_dpm_table;
|
||||
struct vega20_odn_fan_table odn_fan_table;
|
||||
struct vega20_odn_temp_table odn_temp_table;
|
||||
};
|
||||
|
||||
struct vega20_hwmgr {
|
||||
struct vega20_dpm_table dpm_table;
|
||||
struct vega20_dpm_table golden_dpm_table;
|
||||
struct vega20_registry_data registry_data;
|
||||
struct vega20_vbios_boot_state vbios_boot_state;
|
||||
struct vega20_mclk_latency_table mclk_latency_table;
|
||||
|
||||
struct vega20_max_sustainable_clocks max_sustainable_clocks;
|
||||
|
||||
struct vega20_leakage_voltage vddc_leakage;
|
||||
|
||||
uint32_t vddc_control;
|
||||
struct pp_atomfwctrl_voltage_table vddc_voltage_table;
|
||||
uint32_t mvdd_control;
|
||||
struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
|
||||
uint32_t vddci_control;
|
||||
struct pp_atomfwctrl_voltage_table vddci_voltage_table;
|
||||
|
||||
uint32_t active_auto_throttle_sources;
|
||||
struct vega20_bacos bacos;
|
||||
|
||||
/* ---- General data ---- */
|
||||
uint8_t need_update_dpm_table;
|
||||
|
||||
bool cac_enabled;
|
||||
bool battery_state;
|
||||
bool is_tlu_enabled;
|
||||
bool avfs_exist;
|
||||
|
||||
uint32_t low_sclk_interrupt_threshold;
|
||||
|
||||
uint32_t total_active_cus;
|
||||
|
||||
uint32_t water_marks_bitmap;
|
||||
|
||||
struct vega20_display_timing display_timing;
|
||||
|
||||
/* ---- Vega20 Dyn Register Settings ---- */
|
||||
|
||||
uint32_t debug_settings;
|
||||
uint32_t lowest_uclk_reserved_for_ulv;
|
||||
uint32_t gfxclk_average_alpha;
|
||||
uint32_t socclk_average_alpha;
|
||||
uint32_t uclk_average_alpha;
|
||||
uint32_t gfx_activity_average_alpha;
|
||||
uint32_t display_voltage_mode;
|
||||
uint32_t dcef_clk_quad_eqn_a;
|
||||
uint32_t dcef_clk_quad_eqn_b;
|
||||
uint32_t dcef_clk_quad_eqn_c;
|
||||
uint32_t disp_clk_quad_eqn_a;
|
||||
uint32_t disp_clk_quad_eqn_b;
|
||||
uint32_t disp_clk_quad_eqn_c;
|
||||
uint32_t pixel_clk_quad_eqn_a;
|
||||
uint32_t pixel_clk_quad_eqn_b;
|
||||
uint32_t pixel_clk_quad_eqn_c;
|
||||
uint32_t phy_clk_quad_eqn_a;
|
||||
uint32_t phy_clk_quad_eqn_b;
|
||||
uint32_t phy_clk_quad_eqn_c;
|
||||
|
||||
/* ---- Thermal Temperature Setting ---- */
|
||||
struct vega20_dpmlevel_enable_mask dpm_level_enable_mask;
|
||||
|
||||
/* ---- Power Gating States ---- */
|
||||
bool uvd_power_gated;
|
||||
bool vce_power_gated;
|
||||
bool samu_power_gated;
|
||||
bool need_long_memory_training;
|
||||
|
||||
/* Internal settings to apply the application power optimization parameters */
|
||||
bool apply_optimized_settings;
|
||||
uint32_t disable_dpm_mask;
|
||||
|
||||
/* ---- Overdrive next setting ---- */
|
||||
struct vega20_odn_data odn_data;
|
||||
|
||||
/* ---- Workload Mask ---- */
|
||||
uint32_t workload_mask;
|
||||
|
||||
/* ---- SMU9 ---- */
|
||||
uint32_t smu_version;
|
||||
struct smu_features smu_features[GNLD_FEATURES_MAX];
|
||||
struct vega20_smc_state_table smc_state_table;
|
||||
|
||||
/* ---- Gfxoff ---- */
|
||||
bool gfxoff_allowed;
|
||||
uint32_t counter_gfxoff;
|
||||
};
|
||||
|
||||
#define VEGA20_DPM2_NEAR_TDP_DEC 10
|
||||
#define VEGA20_DPM2_ABOVE_SAFE_INC 5
|
||||
#define VEGA20_DPM2_BELOW_SAFE_INC 20
|
||||
|
||||
#define VEGA20_DPM2_LTA_WINDOW_SIZE 7
|
||||
|
||||
#define VEGA20_DPM2_LTS_TRUNCATE 0
|
||||
|
||||
#define VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT 80
|
||||
|
||||
#define VEGA20_DPM2_MAXPS_PERCENT_M 90
|
||||
#define VEGA20_DPM2_MAXPS_PERCENT_H 90
|
||||
|
||||
#define VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN 50
|
||||
|
||||
#define VEGA20_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
|
||||
#define VEGA20_DPM2_SQ_RAMP_MIN_POWER 0x12
|
||||
#define VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
|
||||
#define VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E
|
||||
#define VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF
|
||||
|
||||
#define VEGA20_VOLTAGE_CONTROL_NONE 0x0
|
||||
#define VEGA20_VOLTAGE_CONTROL_BY_GPIO 0x1
|
||||
#define VEGA20_VOLTAGE_CONTROL_BY_SVID2 0x2
|
||||
#define VEGA20_VOLTAGE_CONTROL_MERGED 0x3
|
||||
/* To convert to Q8.8 format for firmware */
|
||||
#define VEGA20_Q88_FORMAT_CONVERSION_UNIT 256
|
||||
|
||||
#define VEGA20_UNUSED_GPIO_PIN 0x7F
|
||||
|
||||
#define VEGA20_THERM_OUT_MODE_DISABLE 0x0
|
||||
#define VEGA20_THERM_OUT_MODE_THERM_ONLY 0x1
|
||||
#define VEGA20_THERM_OUT_MODE_THERM_VRHOT 0x2
|
||||
|
||||
#define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||||
#define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT 0xffffffff
|
||||
|
||||
#define PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff
|
||||
#define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||||
#define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT 0xffffffff
|
||||
|
||||
#define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3
|
||||
#define VEGA20_UMD_PSTATE_SOCCLK_LEVEL 0x3
|
||||
#define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2
|
||||
#define VEGA20_UMD_PSTATE_UVDCLK_LEVEL 0x3
|
||||
#define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL 0x3
|
||||
|
||||
#endif /* _VEGA20_HWMGR_H_ */
|
||||
70
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c
Normal file
70
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c
Normal file
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hwmgr.h"
|
||||
#include "vega20_hwmgr.h"
|
||||
#include "vega20_powertune.h"
|
||||
#include "vega20_smumgr.h"
|
||||
#include "vega20_ppsmc.h"
|
||||
#include "vega20_inc.h"
|
||||
#include "pp_debug.h"
|
||||
|
||||
int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
|
||||
{
|
||||
struct vega20_hwmgr *data =
|
||||
(struct vega20_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (data->smu_features[GNLD_PPT].enabled)
|
||||
return smum_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetPptLimit, n);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr,
|
||||
uint32_t tdp_percentage_adjustment, uint32_t tdp_absolute_value_adjustment)
|
||||
{
|
||||
return (tdp_percentage_adjustment > hwmgr->platform_descriptor.TDPLimit) ? -1 : 0;
|
||||
}
|
||||
|
||||
static int vega20_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
|
||||
uint32_t adjust_percent)
|
||||
{
|
||||
return smum_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
|
||||
}
|
||||
|
||||
int vega20_power_control_set_level(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int adjust_percent, result = 0;
|
||||
|
||||
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
|
||||
adjust_percent =
|
||||
hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
|
||||
hwmgr->platform_descriptor.TDPAdjustment :
|
||||
(-1 * hwmgr->platform_descriptor.TDPAdjustment);
|
||||
result = vega20_set_overdrive_target_percentage(hwmgr,
|
||||
(uint32_t)adjust_percent);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
32
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h
Normal file
32
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _VEGA20_POWERTUNE_H_
|
||||
#define _VEGA20_POWERTUNE_H_
|
||||
|
||||
int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
|
||||
int vega20_power_control_set_level(struct pp_hwmgr *hwmgr);
|
||||
int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr,
|
||||
uint32_t tdp_percentage_adjustment,
|
||||
uint32_t tdp_absolute_value_adjustment);
|
||||
#endif /* _VEGA20_POWERTUNE_H_ */
|
||||
|
||||
919
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
Normal file
919
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
Normal file
@@ -0,0 +1,919 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/fb.h>
|
||||
|
||||
#include "smu11_driver_if.h"
|
||||
#include "vega20_processpptables.h"
|
||||
#include "ppatomfwctrl.h"
|
||||
#include "atomfirmware.h"
|
||||
#include "pp_debug.h"
|
||||
#include "cgs_common.h"
|
||||
#include "vega20_pptable.h"
|
||||
|
||||
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
|
||||
enum phm_platform_caps cap)
|
||||
{
|
||||
if (enable)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
|
||||
else
|
||||
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
|
||||
}
|
||||
|
||||
static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int index = GetIndexIntoMasterDataTable(powerplayinfo);
|
||||
|
||||
u16 size;
|
||||
u8 frev, crev;
|
||||
const void *table_address = hwmgr->soft_pp_table;
|
||||
|
||||
if (!table_address) {
|
||||
table_address = (ATOM_Vega20_POWERPLAYTABLE *)
|
||||
smu_atom_get_data_table(hwmgr->adev, index,
|
||||
&size, &frev, &crev);
|
||||
|
||||
hwmgr->soft_pp_table = table_address;
|
||||
hwmgr->soft_pp_table_size = size;
|
||||
}
|
||||
|
||||
return table_address;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_pptable(PPTable_t *pptable)
|
||||
{
|
||||
int i;
|
||||
|
||||
pr_info("Version = 0x%08x\n", pptable->Version);
|
||||
|
||||
pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
|
||||
pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
|
||||
|
||||
pr_info("SocketPowerLimitAc0 = %d\n", pptable->SocketPowerLimitAc0);
|
||||
pr_info("SocketPowerLimitAc0Tau = %d\n", pptable->SocketPowerLimitAc0Tau);
|
||||
pr_info("SocketPowerLimitAc1 = %d\n", pptable->SocketPowerLimitAc1);
|
||||
pr_info("SocketPowerLimitAc1Tau = %d\n", pptable->SocketPowerLimitAc1Tau);
|
||||
pr_info("SocketPowerLimitAc2 = %d\n", pptable->SocketPowerLimitAc2);
|
||||
pr_info("SocketPowerLimitAc2Tau = %d\n", pptable->SocketPowerLimitAc2Tau);
|
||||
pr_info("SocketPowerLimitAc3 = %d\n", pptable->SocketPowerLimitAc3);
|
||||
pr_info("SocketPowerLimitAc3Tau = %d\n", pptable->SocketPowerLimitAc3Tau);
|
||||
pr_info("SocketPowerLimitDc = %d\n", pptable->SocketPowerLimitDc);
|
||||
pr_info("SocketPowerLimitDcTau = %d\n", pptable->SocketPowerLimitDcTau);
|
||||
pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
|
||||
pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
|
||||
pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
|
||||
pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
|
||||
|
||||
pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
|
||||
pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
|
||||
pr_info("ThbmLimit = %d\n", pptable->ThbmLimit);
|
||||
pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
|
||||
pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
|
||||
pr_info("Tliquid1Limit = %d\n", pptable->Tliquid1Limit);
|
||||
pr_info("Tliquid2Limit = %d\n", pptable->Tliquid2Limit);
|
||||
pr_info("TplxLimit = %d\n", pptable->TplxLimit);
|
||||
pr_info("FitLimit = %d\n", pptable->FitLimit);
|
||||
|
||||
pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
|
||||
pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
|
||||
|
||||
pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage);
|
||||
pr_info("padding8_limits[0] = 0x%02x\n", pptable->padding8_limits[0]);
|
||||
pr_info("padding8_limits[1] = 0x%02x\n", pptable->padding8_limits[1]);
|
||||
pr_info("padding8_limits[2] = 0x%02x\n", pptable->padding8_limits[2]);
|
||||
|
||||
pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc);
|
||||
pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
|
||||
|
||||
pr_info("UlvSmnclkDid = %d\n", pptable->UlvSmnclkDid);
|
||||
pr_info("UlvMp1clkDid = %d\n", pptable->UlvMp1clkDid);
|
||||
pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
|
||||
pr_info("Padding234 = 0x%02x\n", pptable->Padding234);
|
||||
|
||||
pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
|
||||
pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
|
||||
pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
|
||||
pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
|
||||
|
||||
pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
|
||||
pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
|
||||
|
||||
pr_info("[PPCLK_GFXCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_VCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_DCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_ECLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_SOCCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_UCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_DCEFCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_DISPCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_PIXCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_PHYCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.c);
|
||||
|
||||
pr_info("[PPCLK_FCLK]\n"
|
||||
" .VoltageMode = 0x%02x\n"
|
||||
" .SnapToDiscrete = 0x%02x\n"
|
||||
" .NumDiscreteLevels = 0x%02x\n"
|
||||
" .padding = 0x%02x\n"
|
||||
" .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
|
||||
" .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].padding,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
|
||||
pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c);
|
||||
|
||||
|
||||
pr_info("FreqTableGfx\n");
|
||||
for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
|
||||
|
||||
pr_info("FreqTableVclk\n");
|
||||
for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
|
||||
|
||||
pr_info("FreqTableDclk\n");
|
||||
for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
|
||||
|
||||
pr_info("FreqTableEclk\n");
|
||||
for (i = 0; i < NUM_ECLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableEclk[i]);
|
||||
|
||||
pr_info("FreqTableSocclk\n");
|
||||
for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
|
||||
|
||||
pr_info("FreqTableUclk\n");
|
||||
for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
|
||||
|
||||
pr_info("FreqTableFclk\n");
|
||||
for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
|
||||
|
||||
pr_info("FreqTableDcefclk\n");
|
||||
for (i = 0; i < NUM_DCEFCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDcefclk[i]);
|
||||
|
||||
pr_info("FreqTableDispclk\n");
|
||||
for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDispclk[i]);
|
||||
|
||||
pr_info("FreqTablePixclk\n");
|
||||
for (i = 0; i < NUM_PIXCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePixclk[i]);
|
||||
|
||||
pr_info("FreqTablePhyclk\n");
|
||||
for (i = 0; i < NUM_PHYCLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePhyclk[i]);
|
||||
|
||||
pr_info("DcModeMaxFreq[PPCLK_GFXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_VCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_VCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_DCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_ECLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_ECLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_SOCCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_UCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_DCEFCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCEFCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_DISPCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DISPCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_PIXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PIXCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_PHYCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PHYCLK]);
|
||||
pr_info("DcModeMaxFreq[PPCLK_FCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
|
||||
pr_info("Padding8_Clks = %d\n", pptable->Padding8_Clks);
|
||||
|
||||
pr_info("Mp0clkFreq\n");
|
||||
for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
|
||||
|
||||
pr_info("Mp0DpmVoltage\n");
|
||||
for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
|
||||
|
||||
pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
|
||||
pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
|
||||
pr_info("CksEnableFreq = 0x%x\n", pptable->CksEnableFreq);
|
||||
pr_info("Padding789 = 0x%x\n", pptable->Padding789);
|
||||
pr_info("CksVoltageOffset[a = 0x%08x b = 0x%08x c = 0x%08x]\n",
|
||||
pptable->CksVoltageOffset.a,
|
||||
pptable->CksVoltageOffset.b,
|
||||
pptable->CksVoltageOffset.c);
|
||||
pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
|
||||
pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
|
||||
pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
|
||||
pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
|
||||
pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
|
||||
pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
|
||||
pr_info("Padding456 = 0x%x\n", pptable->Padding456);
|
||||
|
||||
pr_info("LowestUclkReservedForUlv = %d\n", pptable->LowestUclkReservedForUlv);
|
||||
pr_info("Padding8_Uclk[0] = 0x%x\n", pptable->Padding8_Uclk[0]);
|
||||
pr_info("Padding8_Uclk[1] = 0x%x\n", pptable->Padding8_Uclk[1]);
|
||||
pr_info("Padding8_Uclk[2] = 0x%x\n", pptable->Padding8_Uclk[2]);
|
||||
|
||||
pr_info("PcieGenSpeed\n");
|
||||
for (i = 0; i < NUM_LINK_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->PcieGenSpeed[i]);
|
||||
|
||||
pr_info("PcieLaneCount\n");
|
||||
for (i = 0; i < NUM_LINK_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
|
||||
|
||||
pr_info("LclkFreq\n");
|
||||
for (i = 0; i < NUM_LINK_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->LclkFreq[i]);
|
||||
|
||||
pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
|
||||
pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
|
||||
pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
|
||||
pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
|
||||
|
||||
pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
|
||||
pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
|
||||
|
||||
pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
|
||||
pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
|
||||
pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid);
|
||||
pr_info("FanGainVrVddc = %d\n", pptable->FanGainVrVddc);
|
||||
pr_info("FanGainVrMvdd = %d\n", pptable->FanGainVrMvdd);
|
||||
pr_info("FanGainPlx = %d\n", pptable->FanGainPlx);
|
||||
pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
|
||||
pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
|
||||
pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
|
||||
pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
|
||||
pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
|
||||
pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
|
||||
pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
|
||||
pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
|
||||
pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
|
||||
|
||||
pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
|
||||
pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
|
||||
pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
|
||||
pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
|
||||
|
||||
pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
|
||||
pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
|
||||
pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
|
||||
pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
|
||||
|
||||
pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
|
||||
pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
|
||||
pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
|
||||
pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
|
||||
pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
|
||||
pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
|
||||
pr_info("dBtcGbGfxCksOn{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->dBtcGbGfxCksOn.a,
|
||||
pptable->dBtcGbGfxCksOn.b,
|
||||
pptable->dBtcGbGfxCksOn.c);
|
||||
pr_info("dBtcGbGfxCksOff{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->dBtcGbGfxCksOff.a,
|
||||
pptable->dBtcGbGfxCksOff.b,
|
||||
pptable->dBtcGbGfxCksOff.c);
|
||||
pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->dBtcGbGfxAfll.a,
|
||||
pptable->dBtcGbGfxAfll.b,
|
||||
pptable->dBtcGbGfxAfll.c);
|
||||
pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->dBtcGbSoc.a,
|
||||
pptable->dBtcGbSoc.b,
|
||||
pptable->dBtcGbSoc.c);
|
||||
pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
|
||||
pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
|
||||
pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
|
||||
pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
|
||||
pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
|
||||
pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
|
||||
|
||||
pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
|
||||
pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
|
||||
pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
|
||||
pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
|
||||
pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
|
||||
pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
|
||||
|
||||
pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
|
||||
pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
|
||||
|
||||
pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
|
||||
pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
|
||||
pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
|
||||
pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
|
||||
|
||||
pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
|
||||
pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
|
||||
pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
|
||||
pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
|
||||
|
||||
pr_info("XgmiLinkSpeed\n");
|
||||
for (i = 0; i < NUM_XGMI_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
|
||||
pr_info("XgmiLinkWidth\n");
|
||||
for (i = 0; i < NUM_XGMI_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
|
||||
pr_info("XgmiFclkFreq\n");
|
||||
for (i = 0; i < NUM_XGMI_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
|
||||
pr_info("XgmiUclkFreq\n");
|
||||
for (i = 0; i < NUM_XGMI_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->XgmiUclkFreq[i]);
|
||||
pr_info("XgmiSocclkFreq\n");
|
||||
for (i = 0; i < NUM_XGMI_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->XgmiSocclkFreq[i]);
|
||||
pr_info("XgmiSocVoltage\n");
|
||||
for (i = 0; i < NUM_XGMI_LEVELS; i++)
|
||||
pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
|
||||
|
||||
pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
|
||||
pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->ReservedEquation0.a,
|
||||
pptable->ReservedEquation0.b,
|
||||
pptable->ReservedEquation0.c);
|
||||
pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->ReservedEquation1.a,
|
||||
pptable->ReservedEquation1.b,
|
||||
pptable->ReservedEquation1.c);
|
||||
pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->ReservedEquation2.a,
|
||||
pptable->ReservedEquation2.b,
|
||||
pptable->ReservedEquation2.c);
|
||||
pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
|
||||
pptable->ReservedEquation3.a,
|
||||
pptable->ReservedEquation3.b,
|
||||
pptable->ReservedEquation3.c);
|
||||
|
||||
pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
|
||||
pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc);
|
||||
|
||||
for (i = 0; i < 14; i++)
|
||||
pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]);
|
||||
|
||||
pr_info("Liquid1_I2C_address = 0x%x\n", pptable->Liquid1_I2C_address);
|
||||
pr_info("Liquid2_I2C_address = 0x%x\n", pptable->Liquid2_I2C_address);
|
||||
pr_info("Vr_I2C_address = 0x%x\n", pptable->Vr_I2C_address);
|
||||
pr_info("Plx_I2C_address = 0x%x\n", pptable->Plx_I2C_address);
|
||||
|
||||
pr_info("Liquid_I2C_LineSCL = 0x%x\n", pptable->Liquid_I2C_LineSCL);
|
||||
pr_info("Liquid_I2C_LineSDA = 0x%x\n", pptable->Liquid_I2C_LineSDA);
|
||||
pr_info("Vr_I2C_LineSCL = 0x%x\n", pptable->Vr_I2C_LineSCL);
|
||||
pr_info("Vr_I2C_LineSDA = 0x%x\n", pptable->Vr_I2C_LineSDA);
|
||||
|
||||
pr_info("Plx_I2C_LineSCL = 0x%x\n", pptable->Plx_I2C_LineSCL);
|
||||
pr_info("Plx_I2C_LineSDA = 0x%x\n", pptable->Plx_I2C_LineSDA);
|
||||
pr_info("VrSensorPresent = 0x%x\n", pptable->VrSensorPresent);
|
||||
pr_info("LiquidSensorPresent = 0x%x\n", pptable->LiquidSensorPresent);
|
||||
|
||||
pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
|
||||
pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
|
||||
|
||||
pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
|
||||
pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
|
||||
pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
|
||||
pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
|
||||
|
||||
pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
|
||||
pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
|
||||
pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
|
||||
pr_info("Padding8_V = 0x%x\n", pptable->Padding8_V);
|
||||
|
||||
pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
|
||||
pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
|
||||
pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
|
||||
|
||||
pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
|
||||
pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
|
||||
pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
|
||||
|
||||
pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
|
||||
pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
|
||||
pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
|
||||
|
||||
pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
|
||||
pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
|
||||
pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
|
||||
|
||||
pr_info("AcDcGpio = %d\n", pptable->AcDcGpio);
|
||||
pr_info("AcDcPolarity = %d\n", pptable->AcDcPolarity);
|
||||
pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
|
||||
pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
|
||||
|
||||
pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
|
||||
pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
|
||||
pr_info("Padding1 = 0x%x\n", pptable->Padding1);
|
||||
pr_info("Padding2 = 0x%x\n", pptable->Padding2);
|
||||
|
||||
pr_info("LedPin0 = %d\n", pptable->LedPin0);
|
||||
pr_info("LedPin1 = %d\n", pptable->LedPin1);
|
||||
pr_info("LedPin2 = %d\n", pptable->LedPin2);
|
||||
pr_info("padding8_4 = 0x%x\n", pptable->padding8_4);
|
||||
|
||||
pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
|
||||
pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
|
||||
pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
|
||||
|
||||
pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
|
||||
pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
|
||||
pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
|
||||
|
||||
pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
|
||||
pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
|
||||
pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
|
||||
|
||||
pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
|
||||
pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
|
||||
pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
|
||||
|
||||
for (i = 0; i < 10; i++)
|
||||
pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
pr_info("MmHubPadding[%d] = 0x%x\n", i, pptable->MmHubPadding[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int check_powerplay_tables(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
const ATOM_Vega20_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
|
||||
ATOM_VEGA20_TABLE_REVISION_VEGA20),
|
||||
"Unsupported PPTable format!", return -1);
|
||||
PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
|
||||
"Invalid PowerPlay Table!", return -1);
|
||||
PP_ASSERT_WITH_CODE(powerplay_table->smcPPTable.Version == PPTABLE_V20_SMU_VERSION,
|
||||
"Unmatch PPTable version, vbios update may be needed!", return -1);
|
||||
|
||||
//dump_pptable(&powerplay_table->smcPPTable);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
|
||||
{
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY),
|
||||
PHM_PlatformCaps_PowerPlaySupport);
|
||||
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
|
||||
PHM_PlatformCaps_BiosPowerSourceControl);
|
||||
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_BACO),
|
||||
PHM_PlatformCaps_BACO);
|
||||
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO),
|
||||
PHM_PlatformCaps_BAMACO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int copy_clock_limits_array(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
uint32_t **pptable_info_array,
|
||||
const uint32_t *pptable_array)
|
||||
{
|
||||
uint32_t array_size, i;
|
||||
uint32_t *table;
|
||||
|
||||
array_size = sizeof(uint32_t) * ATOM_VEGA20_PPCLOCK_COUNT;
|
||||
|
||||
table = kzalloc(array_size, GFP_KERNEL);
|
||||
if (NULL == table)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ATOM_VEGA20_PPCLOCK_COUNT; i++)
|
||||
table[i] = pptable_array[i];
|
||||
|
||||
*pptable_info_array = table;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int copy_overdrive_settings_limits_array(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
uint32_t **pptable_info_array,
|
||||
const uint32_t *pptable_array)
|
||||
{
|
||||
uint32_t array_size, i;
|
||||
uint32_t *table;
|
||||
|
||||
array_size = sizeof(uint32_t) * ATOM_VEGA20_ODSETTING_COUNT;
|
||||
|
||||
table = kzalloc(array_size, GFP_KERNEL);
|
||||
if (NULL == table)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ATOM_VEGA20_ODSETTING_COUNT; i++)
|
||||
table[i] = pptable_array[i];
|
||||
|
||||
*pptable_info_array = table;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
|
||||
{
|
||||
struct atom_smc_dpm_info_v4_3 *smc_dpm_table;
|
||||
int index = GetIndexIntoMasterDataTable(smc_dpm_info);
|
||||
|
||||
PP_ASSERT_WITH_CODE(
|
||||
smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL),
|
||||
"[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
|
||||
return -1);
|
||||
|
||||
ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table->liquid1_i2c_address;
|
||||
ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table->liquid2_i2c_address;
|
||||
ppsmc_pptable->Vr_I2C_address = smc_dpm_table->vr_i2c_address;
|
||||
ppsmc_pptable->Plx_I2C_address = smc_dpm_table->plx_i2c_address;
|
||||
|
||||
ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table->liquid_i2c_linescl;
|
||||
ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table->liquid_i2c_linesda;
|
||||
ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table->vr_i2c_linescl;
|
||||
ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table->vr_i2c_linesda;
|
||||
|
||||
ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table->plx_i2c_linescl;
|
||||
ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table->plx_i2c_linesda;
|
||||
ppsmc_pptable->VrSensorPresent = smc_dpm_table->vrsensorpresent;
|
||||
ppsmc_pptable->LiquidSensorPresent = smc_dpm_table->liquidsensorpresent;
|
||||
|
||||
ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
|
||||
ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
|
||||
|
||||
ppsmc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
|
||||
ppsmc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
|
||||
ppsmc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
|
||||
ppsmc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
|
||||
|
||||
ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
|
||||
ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
|
||||
ppsmc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
|
||||
|
||||
ppsmc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
|
||||
ppsmc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
|
||||
ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
|
||||
|
||||
ppsmc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
|
||||
ppsmc_pptable->SocOffset = smc_dpm_table->socoffset;
|
||||
ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
|
||||
|
||||
ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
|
||||
ppsmc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
|
||||
ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
|
||||
|
||||
ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
|
||||
ppsmc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
|
||||
ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
|
||||
|
||||
ppsmc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
|
||||
ppsmc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
|
||||
ppsmc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
|
||||
ppsmc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
|
||||
|
||||
ppsmc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
|
||||
ppsmc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
|
||||
ppsmc_pptable->Padding1 = smc_dpm_table->padding1;
|
||||
ppsmc_pptable->Padding2 = smc_dpm_table->padding2;
|
||||
|
||||
ppsmc_pptable->LedPin0 = smc_dpm_table->ledpin0;
|
||||
ppsmc_pptable->LedPin1 = smc_dpm_table->ledpin1;
|
||||
ppsmc_pptable->LedPin2 = smc_dpm_table->ledpin2;
|
||||
|
||||
ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
|
||||
ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
|
||||
ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
|
||||
|
||||
ppsmc_pptable->UclkSpreadEnabled = 0;
|
||||
ppsmc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
|
||||
ppsmc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
|
||||
|
||||
ppsmc_pptable->FclkSpreadEnabled = 0;
|
||||
ppsmc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
|
||||
ppsmc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
|
||||
|
||||
ppsmc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
|
||||
ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
|
||||
ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define VEGA20_ENGINECLOCK_HARDMAX 198000
|
||||
static int init_powerplay_table_information(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
const ATOM_Vega20_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
struct phm_ppt_v3_information *pptable_information =
|
||||
(struct phm_ppt_v3_information *)hwmgr->pptable;
|
||||
uint32_t disable_power_control = 0;
|
||||
int result;
|
||||
|
||||
hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
|
||||
pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
|
||||
|
||||
set_hw_cap(hwmgr,
|
||||
ATOM_VEGA20_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
|
||||
PHM_PlatformCaps_ThermalController);
|
||||
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
|
||||
|
||||
if (powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_GFXCLKFMAX] > VEGA20_ENGINECLOCK_HARDMAX)
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA20_ENGINECLOCK_HARDMAX;
|
||||
else
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock = powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_GFXCLKFMAX];
|
||||
hwmgr->platform_descriptor.overdriveLimit.memoryClock = powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_UCLKFMAX];
|
||||
|
||||
copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_max, powerplay_table->OverDrive8Table.ODSettingsMax);
|
||||
copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_min, powerplay_table->OverDrive8Table.ODSettingsMin);
|
||||
|
||||
/* hwmgr->platformDescriptor.minOverdriveVDDC = 0;
|
||||
hwmgr->platformDescriptor.maxOverdriveVDDC = 0;
|
||||
hwmgr->platformDescriptor.overdriveVDDCStep = 0; */
|
||||
|
||||
if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
|
||||
&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
|
||||
|
||||
pptable_information->us_small_power_limit1 = powerplay_table->usSmallPowerLimit1;
|
||||
pptable_information->us_small_power_limit2 = powerplay_table->usSmallPowerLimit2;
|
||||
pptable_information->us_boost_power_limit = powerplay_table->usBoostPowerLimit;
|
||||
pptable_information->us_od_turbo_power_limit = powerplay_table->usODTurboPowerLimit;
|
||||
pptable_information->us_od_powersave_power_limit = powerplay_table->usODPowerSavePowerLimit;
|
||||
|
||||
pptable_information->us_software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
|
||||
|
||||
hwmgr->platform_descriptor.TDPODLimit = (uint16_t)powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE];
|
||||
|
||||
disable_power_control = 0;
|
||||
if (!disable_power_control && hwmgr->platform_descriptor.TDPODLimit) {
|
||||
/* enable TDP overdrive (PowerControl) feature as well if supported */
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_PowerControl);
|
||||
}
|
||||
|
||||
copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockTable.PowerSavingClockMax);
|
||||
copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockTable.PowerSavingClockMin);
|
||||
|
||||
pptable_information->smc_pptable = (PPTable_t *)kmalloc(sizeof(PPTable_t), GFP_KERNEL);
|
||||
if (pptable_information->smc_pptable == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t));
|
||||
|
||||
result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int vega20_pp_tables_initialize(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int result = 0;
|
||||
const ATOM_Vega20_POWERPLAYTABLE *powerplay_table;
|
||||
|
||||
hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
|
||||
PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
|
||||
"Failed to allocate hwmgr->pptable!", return -ENOMEM);
|
||||
|
||||
powerplay_table = get_powerplay_table(hwmgr);
|
||||
PP_ASSERT_WITH_CODE((powerplay_table != NULL),
|
||||
"Missing PowerPlay Table!", return -1);
|
||||
|
||||
result = check_powerplay_tables(hwmgr, powerplay_table);
|
||||
PP_ASSERT_WITH_CODE((result == 0),
|
||||
"check_powerplay_tables failed", return result);
|
||||
|
||||
result = set_platform_caps(hwmgr,
|
||||
le32_to_cpu(powerplay_table->ulPlatformCaps));
|
||||
PP_ASSERT_WITH_CODE((result == 0),
|
||||
"set_platform_caps failed", return result);
|
||||
|
||||
result = init_powerplay_table_information(hwmgr, powerplay_table);
|
||||
PP_ASSERT_WITH_CODE((result == 0),
|
||||
"init_powerplay_table_information failed", return result);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int vega20_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct phm_ppt_v3_information *pp_table_info =
|
||||
(struct phm_ppt_v3_information *)(hwmgr->pptable);
|
||||
|
||||
kfree(pp_table_info->power_saving_clock_max);
|
||||
pp_table_info->power_saving_clock_max = NULL;
|
||||
|
||||
kfree(pp_table_info->power_saving_clock_min);
|
||||
pp_table_info->power_saving_clock_min = NULL;
|
||||
|
||||
kfree(pp_table_info->od_settings_max);
|
||||
pp_table_info->od_settings_max = NULL;
|
||||
|
||||
kfree(pp_table_info->od_settings_min);
|
||||
pp_table_info->od_settings_min = NULL;
|
||||
|
||||
kfree(pp_table_info->smc_pptable);
|
||||
pp_table_info->smc_pptable = NULL;
|
||||
|
||||
kfree(hwmgr->pptable);
|
||||
hwmgr->pptable = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct pp_table_func vega20_pptable_funcs = {
|
||||
.pptable_init = vega20_pp_tables_initialize,
|
||||
.pptable_fini = vega20_pp_tables_uninitialize,
|
||||
};
|
||||
31
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.h
Normal file
31
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef VEGA20_PROCESSPPTABLES_H
|
||||
#define VEGA20_PROCESSPPTABLES_H
|
||||
|
||||
#include "hwmgr.h"
|
||||
|
||||
extern const struct pp_table_func vega20_pptable_funcs;
|
||||
|
||||
#endif
|
||||
212
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c
Normal file
212
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c
Normal file
@@ -0,0 +1,212 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "vega20_thermal.h"
|
||||
#include "vega20_hwmgr.h"
|
||||
#include "vega20_smumgr.h"
|
||||
#include "vega20_ppsmc.h"
|
||||
#include "vega20_inc.h"
|
||||
#include "soc15_common.h"
|
||||
#include "pp_debug.h"
|
||||
|
||||
static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
|
||||
PPSMC_MSG_GetCurrentRpm)) == 0,
|
||||
"Attempt to get current RPM from SMC Failed!",
|
||||
return ret);
|
||||
PP_ASSERT_WITH_CODE((ret = vega20_read_arg_from_smc(hwmgr,
|
||||
current_rpm)) == 0,
|
||||
"Attempt to read current RPM from SMC Failed!",
|
||||
return ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||
struct phm_fan_speed_info *fan_speed_info)
|
||||
{
|
||||
memset(fan_speed_info, 0, sizeof(*fan_speed_info));
|
||||
fan_speed_info->supports_percent_read = false;
|
||||
fan_speed_info->supports_percent_write = false;
|
||||
fan_speed_info->supports_rpm_read = true;
|
||||
fan_speed_info->supports_rpm_write = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
|
||||
{
|
||||
*speed = 0;
|
||||
|
||||
return vega20_get_current_rpm(hwmgr, speed);
|
||||
}
|
||||
|
||||
/**
|
||||
* Reads the remote temperature from the SIslands thermal controller.
|
||||
*
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
int temp = 0;
|
||||
|
||||
temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
|
||||
|
||||
temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
|
||||
CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
|
||||
|
||||
temp = temp & 0x1ff;
|
||||
|
||||
temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the requested temperature range for high and low alert signals
|
||||
*
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
* @param range Temperature range to be programmed for
|
||||
* high and low alert signals
|
||||
* @exception PP_Result_BadInput if the input data is not valid.
|
||||
*/
|
||||
static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
|
||||
struct PP_TemperatureRange *range)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP *
|
||||
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP *
|
||||
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
uint32_t val;
|
||||
|
||||
if (low < range->min)
|
||||
low = range->min;
|
||||
if (high > range->max)
|
||||
high = range->max;
|
||||
|
||||
if (low > high)
|
||||
return -EINVAL;
|
||||
|
||||
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
|
||||
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
|
||||
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
|
||||
|
||||
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable thermal alerts on the RV770 thermal controller.
|
||||
*
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
static int vega20_thermal_enable_alert(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t val = 0;
|
||||
|
||||
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
|
||||
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
|
||||
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
|
||||
|
||||
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable thermal alerts on the RV770 thermal controller.
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
|
||||
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Uninitialize the thermal controller.
|
||||
* Currently just disables alerts.
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int result = vega20_thermal_disable_alert(hwmgr);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set up the fan table to control the fan using the SMC.
|
||||
* @param hwmgr the address of the powerplay hardware manager.
|
||||
* @param pInput the pointer to input data
|
||||
* @param pOutput the pointer to output data
|
||||
* @param pStorage the pointer to temporary storage
|
||||
* @param Result the last failure code
|
||||
* @return result from set temperature range routine
|
||||
*/
|
||||
static int vega20_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int ret;
|
||||
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
|
||||
PPTable_t *table = &(data->smc_state_table.pp_table);
|
||||
|
||||
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetFanTemperatureTarget,
|
||||
(uint32_t)table->FanTargetTemperature);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
|
||||
struct PP_TemperatureRange *range)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (range == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
ret = vega20_thermal_set_temperature_range(hwmgr, range);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = vega20_thermal_enable_alert(hwmgr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = vega20_thermal_setup_fan_table(hwmgr);
|
||||
|
||||
return ret;
|
||||
};
|
||||
64
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h
Normal file
64
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef VEGA20_THERMAL_H
|
||||
#define VEGA20_THERMAL_H
|
||||
|
||||
#include "hwmgr.h"
|
||||
|
||||
struct vega20_temperature {
|
||||
uint16_t edge_temp;
|
||||
uint16_t hot_spot_temp;
|
||||
uint16_t hbm_temp;
|
||||
uint16_t vr_soc_temp;
|
||||
uint16_t vr_mem_temp;
|
||||
uint16_t liquid1_temp;
|
||||
uint16_t liquid2_temp;
|
||||
uint16_t plx_temp;
|
||||
};
|
||||
|
||||
#define VEGA20_THERMAL_HIGH_ALERT_MASK 0x1
|
||||
#define VEGA20_THERMAL_LOW_ALERT_MASK 0x2
|
||||
|
||||
#define VEGA20_THERMAL_MINIMUM_TEMP_READING -256
|
||||
#define VEGA20_THERMAL_MAXIMUM_TEMP_READING 255
|
||||
|
||||
#define VEGA20_THERMAL_MINIMUM_ALERT_TEMP 0
|
||||
#define VEGA20_THERMAL_MAXIMUM_ALERT_TEMP 255
|
||||
|
||||
#define FDO_PWM_MODE_STATIC 1
|
||||
#define FDO_PWM_MODE_STATIC_RPM 5
|
||||
|
||||
extern int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr);
|
||||
extern int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
|
||||
extern int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||
struct phm_fan_speed_info *fan_speed_info);
|
||||
extern int vega20_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
|
||||
extern int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
|
||||
uint32_t *speed);
|
||||
extern int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr);
|
||||
extern int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
|
||||
struct PP_TemperatureRange *range);
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user