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MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)

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The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.

Signed-off-by: Al Cooper <alcooperx@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Al Cooper
2012-07-13 16:44:51 -04:00
committed by Ralf Baechle
parent c5600b2dd9
commit da4b62cd67
5 changed files with 13 additions and 3 deletions
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4
arch/mips/include/asm/cpu-features.h
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@@ -252,4 +252,8 @@
#define cpu_hwrena_impl_bits 0
#endif
#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
#endif
#endif /* __ASM_CPU_FEATURES_H */