[ARM] OMAP2 PRCM: clean up CM_IDLEST bits
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly marked as being OMAP2xxx-wide, when they were actually 2420-specific. Also, originally when the PRCM register macros were defined, bit shift macros used a "_SHIFT" suffix, and mask macros used none. This became a source of bugs and confusion, as the mask macros were mistakenly used for shift values. Gradually, the mask macros have been updated, piece by piece, to add a "_MASK" suffix on the end to clarify. This patch applies this change to the CM_IDLEST_* register bits. The patch also adds a few bits that were missing, mostly from the 3430ES1 to ES2 revisions. linux-omap source commits are d18eff5b5fa15e170794397a6a94486d1f774f77, e1f1a5cc24615fb790cc763c96d1c5cfe6296f5b, and part of 9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1 Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Paul Walmsley
committad av
Russell King
Russell King
förälder
027d8ded5d
incheckning
da0747d4fa
@@ -183,29 +183,52 @@
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#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
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/* CM_IDLEST1_CORE specific bits */
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#define OMAP3430_ST_ICR (1 << 29)
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#define OMAP3430_ST_AES2 (1 << 28)
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#define OMAP3430_ST_SHA12 (1 << 27)
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#define OMAP3430_ST_DES2 (1 << 26)
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#define OMAP3430_ST_MSPRO (1 << 23)
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#define OMAP3430_ST_HDQ (1 << 22)
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#define OMAP3430ES1_ST_FAC (1 << 8)
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#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
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#define OMAP3430_ST_OMAPCTRL (1 << 6)
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#define OMAP3430_ST_SDMA (1 << 2)
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#define OMAP3430_ST_SDRC (1 << 1)
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#define OMAP3430_ST_SSI (1 << 0)
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#define OMAP3430ES2_ST_MMC3_SHIFT 30
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#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
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#define OMAP3430_ST_ICR_SHIFT 29
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#define OMAP3430_ST_ICR_MASK (1 << 29)
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#define OMAP3430_ST_AES2_SHIFT 28
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#define OMAP3430_ST_AES2_MASK (1 << 28)
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#define OMAP3430_ST_SHA12_SHIFT 27
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#define OMAP3430_ST_SHA12_MASK (1 << 27)
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#define OMAP3430_ST_DES2_SHIFT 26
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#define OMAP3430_ST_DES2_MASK (1 << 26)
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#define OMAP3430_ST_MSPRO_SHIFT 23
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#define OMAP3430_ST_MSPRO_MASK (1 << 23)
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#define OMAP3430_ST_HDQ_SHIFT 22
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#define OMAP3430_ST_HDQ_MASK (1 << 22)
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#define OMAP3430ES1_ST_FAC_SHIFT 8
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#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
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#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
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#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
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#define OMAP3430_ST_MAILBOXES_SHIFT 7
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#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
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#define OMAP3430_ST_OMAPCTRL_SHIFT 6
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#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
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#define OMAP3430_ST_SDMA_SHIFT 2
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#define OMAP3430_ST_SDMA_MASK (1 << 2)
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#define OMAP3430_ST_SDRC_SHIFT 1
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#define OMAP3430_ST_SDRC_MASK (1 << 1)
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#define OMAP3430_ST_SSI_STDBY_SHIFT 0
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#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
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/* CM_IDLEST2_CORE */
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#define OMAP3430_ST_PKA (1 << 4)
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#define OMAP3430_ST_AES1 (1 << 3)
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#define OMAP3430_ST_RNG (1 << 2)
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#define OMAP3430_ST_SHA11 (1 << 1)
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#define OMAP3430_ST_DES1 (1 << 0)
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#define OMAP3430_ST_PKA_SHIFT 4
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#define OMAP3430_ST_PKA_MASK (1 << 4)
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#define OMAP3430_ST_AES1_SHIFT 3
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#define OMAP3430_ST_AES1_MASK (1 << 3)
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#define OMAP3430_ST_RNG_SHIFT 2
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#define OMAP3430_ST_RNG_MASK (1 << 2)
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#define OMAP3430_ST_SHA11_SHIFT 1
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#define OMAP3430_ST_SHA11_MASK (1 << 1)
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#define OMAP3430_ST_DES1_SHIFT 0
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#define OMAP3430_ST_DES1_MASK (1 << 0)
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/* CM_IDLEST3_CORE */
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#define OMAP3430ES2_ST_USBTLL_SHIFT 2
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#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
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#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
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#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
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/* CM_AUTOIDLE1_CORE */
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#define OMAP3430ES2_AUTO_MMC3 (1 << 30)
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@@ -360,6 +383,7 @@
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/* CM_FCLKEN_WKUP specific bits */
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#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
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#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
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/* CM_ICLKEN_WKUP specific bits */
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#define OMAP3430_EN_WDT1 (1 << 4)
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@@ -368,11 +392,18 @@
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#define OMAP3430_EN_32KSYNC_SHIFT 2
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/* CM_IDLEST_WKUP specific bits */
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#define OMAP3430_ST_WDT2 (1 << 5)
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#define OMAP3430_ST_WDT1 (1 << 4)
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#define OMAP3430_ST_32KSYNC (1 << 2)
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#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
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#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
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#define OMAP3430_ST_WDT2_SHIFT 5
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#define OMAP3430_ST_WDT2_MASK (1 << 5)
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#define OMAP3430_ST_WDT1_SHIFT 4
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#define OMAP3430_ST_WDT1_MASK (1 << 4)
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#define OMAP3430_ST_32KSYNC_SHIFT 2
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#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
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/* CM_AUTOIDLE_WKUP */
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#define OMAP3430ES2_AUTO_USIMOCP (1 << 9)
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#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
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#define OMAP3430_AUTO_WDT2 (1 << 5)
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#define OMAP3430_AUTO_WDT2_SHIFT 5
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#define OMAP3430_AUTO_WDT1 (1 << 4)
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@@ -437,6 +468,8 @@
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#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
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/* CM_IDLEST2_CKGEN */
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#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
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#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
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#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
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#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
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#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
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@@ -508,7 +541,12 @@
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#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
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/* CM_IDLEST_DSS */
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#define OMAP3430_ST_DSS (1 << 0)
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#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
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#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
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#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
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#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
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#define OMAP3430ES1_ST_DSS_SHIFT 0
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#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
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/* CM_AUTOIDLE_DSS */
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#define OMAP3430_AUTO_DSS (1 << 0)
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@@ -562,10 +600,14 @@
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/* CM_ICLKEN_PER specific bits */
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/* CM_IDLEST_PER */
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#define OMAP3430_ST_WDT3 (1 << 12)
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#define OMAP3430_ST_MCBSP4 (1 << 2)
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#define OMAP3430_ST_MCBSP3 (1 << 1)
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#define OMAP3430_ST_MCBSP2 (1 << 0)
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#define OMAP3430_ST_WDT3_SHIFT 12
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#define OMAP3430_ST_WDT3_MASK (1 << 12)
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#define OMAP3430_ST_MCBSP4_SHIFT 2
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#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
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#define OMAP3430_ST_MCBSP3_SHIFT 1
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#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
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#define OMAP3430_ST_MCBSP2_SHIFT 0
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#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
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/* CM_AUTOIDLE_PER */
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#define OMAP3430_AUTO_GPIO6 (1 << 17)
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@@ -693,6 +735,10 @@
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#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
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/* CM_IDLEST_USBHOST */
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#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
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#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
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#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
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#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
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/* CM_AUTOIDLE_USBHOST */
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#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
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