drm/radeon/kms: move a bunch of modesetting debug to correct debug usage.
This migrates a bunch of DRM_DEBUG->DRM_DEBUG_KMS so we can get more modesetting related info without all the other ioctl handling easily. Also the PM code moves to DRM_DEBUG_DRIVER mostly. Signed-off-by: Dave Airlie <airlied@redhat.com>
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@@ -141,7 +141,7 @@ void r100_pm_get_dynpm_state(struct radeon_device *rdev)
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/* only one clock mode per power state */
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rdev->pm.requested_clock_mode_index = 0;
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DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
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DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
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rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].sclk,
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rdev->pm.power_state[rdev->pm.requested_power_state_index].
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@@ -276,7 +276,7 @@ void r100_pm_misc(struct radeon_device *rdev)
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rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
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radeon_set_pcie_lanes(rdev,
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ps->pcie_lanes);
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DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
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DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
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}
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}
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@@ -849,7 +849,7 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
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const char *fw_name = NULL;
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int err;
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DRM_DEBUG("\n");
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DRM_DEBUG_KMS("\n");
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pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
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err = IS_ERR(pdev);
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@@ -2642,7 +2642,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
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flags |= pitch / 8;
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DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
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DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
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WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
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WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
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WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
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@@ -3038,7 +3038,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
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}
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#endif
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DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
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DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
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/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
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(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
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}
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@@ -3134,7 +3134,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
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WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
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}
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DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
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DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
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(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
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}
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}
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