Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Paul Burton: - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB (GINVT) instructions, allowing for more efficient TLB maintenance when running on a CPU such as the I6500 that supports these. - Enable huge page support for MIPS64r6. - Optimize post-DMA cache sync by removing that code entirely for kernel configurations in which we know it won't be needed. - The number of pages allocated for interrupt stacks is now calculated correctly, where before we would wastefully allocate too much memory in some configurations. - The ath79 platform migrates to devicetree. - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board. - The ingenic/jz4740 platform gains support for appended devicetrees. - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see cleanups as do various pieces of core architecture code. * tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits) MIPS: lantiq: Remove separate GPHY Firmware loader MIPS: ingenic: Add support for appended devicetree MIPS: SGI-IP27: rework HUB interrupts MIPS: SGI-IP27: do boot CPU init later MIPS: SGI-IP27: do xtalk scanning later MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output MIPS: SGI-IP27: clean up bridge access and header files MIPS: SGI-IP27: get rid of volatile and hubreg_t MIPS: irq: Allocate accurate order pages for irq stack MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys() MIPS: eBPF: Remove REG_32BIT_ZERO_EX MIPS: eBPF: Always return sign extended 32b values MIPS: CM: Fix indentation MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support MIPS: OCTEON: program rx/tx-delay always from DT MIPS: OCTEON: delete board-specific link status MIPS: OCTEON: don't lie about interface type of CN3005 board MIPS: OCTEON: warn if deprecated link status is being used MIPS: OCTEON: add fixed-link nodes to in-kernel device tree MIPS: Delete unused flush_cache_sigtramp() ...
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@@ -1,36 +0,0 @@
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Lantiq XWAY SoC GPHY binding
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============================
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This binding describes a software-defined ethernet PHY, provided by the RCU
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module on newer Lantiq XWAY SoCs (xRX200 and newer).
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,xrx200a1x-gphy"
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"lantiq,xrx200a2x-gphy"
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"lantiq,xrx300-gphy"
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"lantiq,xrx330-gphy"
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- reg : Addrress of the GPHY FW load address register
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- resets : Must reference the RCU GPHY reset bit
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- reset-names : One entry, value must be "gphy" or optional "gphy2"
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- clocks : A reference to the (PMU) GPHY clock gate
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Optional properties:
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- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
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<dt-bindings/mips/lantiq_xway_gphy.h>
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-------------------------------------------------------------------------------
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Example for the GPHys on the xRX200 SoCs:
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#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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@@ -26,24 +26,6 @@ Example of the RCU bindings on a xRX200 SoC:
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ranges = <0x0 0x203000 0x100>;
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big-endian;
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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gphy1: gphy@68 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x68 0x4>;
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resets = <&reset0 29 28>, <&reset1 6 6>;
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reset-names = "gphy", "gphy2";
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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reset0: reset-controller@10 {
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compatible = "lantiq,xrx200-reset";
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reg = <0x10 4>, <0x14 4>;
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