drm/radeon: initial VCE support v4
Only VCE 2.0 support so far. v2: squashing multiple patches into this one v3: add IRQ support for CIK, major cleanups, basic code documentation v4: remove HAINAN from chipset list Signed-off-by: Christian König <christian.koenig@amd.com>
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@@ -7490,6 +7490,20 @@ restart_ih:
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/* reset addr and status */
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WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
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break;
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case 167: /* VCE */
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DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
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switch (src_data) {
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case 0:
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radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
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break;
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case 1:
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radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
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break;
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default:
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DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
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break;
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}
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break;
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case 176: /* GFX RB CP_INT */
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case 177: /* GFX IB CP_INT */
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radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
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@@ -7789,6 +7803,22 @@ static int cik_startup(struct radeon_device *rdev)
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if (r)
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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r = radeon_vce_resume(rdev);
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if (!r) {
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r = vce_v2_0_resume(rdev);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE1_INDEX);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE2_INDEX);
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}
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if (r) {
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dev_err(rdev->dev, "VCE init error (%d).\n", r);
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rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
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rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
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}
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/* Enable IRQ */
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if (!rdev->irq.installed) {
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r = radeon_irq_kms_init(rdev);
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@@ -7864,6 +7894,23 @@ static int cik_startup(struct radeon_device *rdev)
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DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
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}
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r = -ENOENT;
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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VCE_CMD_NO_OP);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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VCE_CMD_NO_OP);
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if (!r)
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r = vce_v1_0_init(rdev);
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else if (r != -ENOENT)
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DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@@ -7934,6 +7981,7 @@ int cik_suspend(struct radeon_device *rdev)
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cik_sdma_enable(rdev, false);
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uvd_v1_0_fini(rdev);
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radeon_uvd_suspend(rdev);
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radeon_vce_suspend(rdev);
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cik_fini_pg(rdev);
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cik_fini_cg(rdev);
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cik_irq_suspend(rdev);
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@@ -8066,6 +8114,17 @@ int cik_init(struct radeon_device *rdev)
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r600_ring_init(rdev, ring, 4096);
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}
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r = radeon_vce_init(rdev);
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if (!r) {
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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}
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@@ -8127,6 +8186,7 @@ void cik_fini(struct radeon_device *rdev)
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radeon_irq_kms_fini(rdev);
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uvd_v1_0_fini(rdev);
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radeon_uvd_fini(rdev);
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radeon_vce_fini(rdev);
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cik_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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