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clk: qcom: ipq4019: Add the apss cpu pll divider clock node

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The current ipq4019 clock driver does not have support for all
the frequency supported by APSS CPU. APSS CPU frequency is
provided with APSS CPU PLL divider which divides down the VCO
frequency. This divider is nonlinear and specific to IPQ4019
so the standard divider code cannot be used for this.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Abhishek Sahu
2016-11-25 21:11:29 +05:30
committed by Stephen Boyd
parent 4577aa01a5
commit d83dcacea1
2 changed files with 133 additions and 0 deletions
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1
include/dt-bindings/clock/qcom,gcc-ipq4019.h
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@@ -90,6 +90,7 @@
#define GCC_FEPLL500_CLK 71
#define GCC_FEPLL_WCSS2G_CLK 72
#define GCC_FEPLL_WCSS5G_CLK 73
#define GCC_APSS_CPU_PLLDIV_CLK 74
#define WIFI0_CPU_INIT_RESET 0
#define WIFI0_RADIO_SRIF_RESET 1