Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung

Samsung clock patches for 3.17

1) non-critical fixes (without need to push to stable):

d5e136a clk: samsung: Register clk provider only after registering its all clocks
305cfab clk: samsung: Make of_device_id array const
e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend
f65d518 clk: samsung: trivial: Correct typo in author's name

2) Exynos CLKOUT driver:

800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy
1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data

3) Clock hierarchy extensions:

17d3f1d clk: exynos4: Add PPMU IP block source clocks.
ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data

4) ARM CLKDOWN functionality enablement for Exynos4 and 3250:

42773b2 clk: samsung: exynos4: Enable ARMCLK down feature
45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature
This commit is contained in:
Mike Turquette
2014-07-31 09:32:18 -07:00
24 changed files with 599 additions and 19 deletions

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@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -34,6 +34,11 @@
#define CLK_MOUT_CORE 19
#define CLK_MOUT_APLL 20
#define CLK_SCLK_HDMIPHY 22
#define CLK_OUT_DMC 23
#define CLK_OUT_TOP 24
#define CLK_OUT_LEFTBUS 25
#define CLK_OUT_RIGHTBUS 26
#define CLK_OUT_CPU 27
/* gate for special clocks (sclk) */
#define CLK_SCLK_FIMC0 128
@@ -230,6 +235,24 @@
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400
#define CLK_PPMURIGHT 401
#define CLK_PPMUCAMIF 402
#define CLK_PPMUTV 403
#define CLK_PPMUMFC_L 404
#define CLK_PPMUMFC_R 405
#define CLK_PPMUG3D 406
#define CLK_PPMUIMAGE 407
#define CLK_PPMULCD0 408
#define CLK_PPMULCD1 409 /* Exynos4210 only */
#define CLK_PPMUFILE 410
#define CLK_PPMUGPS 411
#define CLK_PPMUDMC0 412
#define CLK_PPMUDMC1 413
#define CLK_PPMUCPU 414
#define CLK_PPMUACP 415
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */

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@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as