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drm/amd/display: fix missing writeback disablement if plane is removed

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[ Upstream commit 82367e7f22d085092728f45fd5fbb15e3fb997c0 ]

[Why]
If the plane has been removed, the writeback disablement logic
doesn't run

[How]
fix the logic order

Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Roy Chan
2021-07-21 19:33:26 -04:00
committed by Greg Kroah-Hartman
parent 491c8be219
commit d763afc4ea
2 changed files with 19 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@@ -1704,15 +1704,17 @@ void dcn20_program_front_end_for_ctx(
dcn20_program_pipe(dc, pipe, context); dcn20_program_pipe(dc, pipe, context);
pipe = pipe->bottom_pipe; pipe = pipe->bottom_pipe;
} }
}
/* Program secondary blending tree and writeback pipes */ /* Program secondary blending tree and writeback pipes */
pipe = &context->res_ctx.pipe_ctx[i]; pipe = &context->res_ctx.pipe_ctx[i];
if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0 if (!pipe->top_pipe && !pipe->prev_odm_pipe
&& (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw) && pipe->stream && pipe->stream->num_wb_info > 0
&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
|| pipe->stream->update_flags.raw)
&& hws->funcs.program_all_writeback_pipes_in_tree) && hws->funcs.program_all_writeback_pipes_in_tree)
hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
} }
} }
}
void dcn20_post_unlock_program_front_end( void dcn20_post_unlock_program_front_end(
struct dc *dc, struct dc *dc,

12
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View File

@@ -396,12 +396,22 @@ void dcn30_program_all_writeback_pipes_in_tree(
for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
if (!pipe_ctx->plane_state)
continue;
if (pipe_ctx->plane_state == wb_info.writeback_source_plane) { if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
break; break;
} }
} }
ASSERT(wb_info.mpcc_inst != -1);
if (wb_info.mpcc_inst == -1) {
/* Disable writeback pipe and disconnect from MPCC
* if source plane has been removed
*/
dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
continue;
}
ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];