Merge branch 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 core updates from Ingo Molnar:
"There were so many changes in the x86/asm, x86/apic and x86/mm topics
in this cycle that the topical separation of -tip broke down somewhat -
so the result is a more traditional architecture pull request,
collected into the 'x86/core' topic.
The topics were still maintained separately as far as possible, so
bisectability and conceptual separation should still be pretty good -
but there were a handful of merge points to avoid excessive
dependencies (and conflicts) that would have been poorly tested in the
end.
The next cycle will hopefully be much more quiet (or at least will
have fewer dependencies).
The main changes in this cycle were:
* x86/apic changes, with related IRQ core changes: (Jiang Liu, Thomas
Gleixner)
- This is the second and most intrusive part of changes to the x86
interrupt handling - full conversion to hierarchical interrupt
domains:
[IOAPIC domain] -----
|
[MSI domain] --------[Remapping domain] ----- [ Vector domain ]
| (optional) |
[HPET MSI domain] ----- |
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[DMAR domain] -----------------------------
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[Legacy domain] -----------------------------
This now reflects the actual hardware and allowed us to distangle
the domain specific code from the underlying parent domain, which
can be optional in the case of interrupt remapping. It's a clear
separation of functionality and removes quite some duct tape
constructs which plugged the remap code between ioapic/msi/hpet
and the vector management.
- Intel IOMMU IRQ remapping enhancements, to allow direct interrupt
injection into guests (Feng Wu)
* x86/asm changes:
- Tons of cleanups and small speedups, micro-optimizations. This
is in preparation to move a good chunk of the low level entry
code from assembly to C code (Denys Vlasenko, Andy Lutomirski,
Brian Gerst)
- Moved all system entry related code to a new home under
arch/x86/entry/ (Ingo Molnar)
- Removal of the fragile and ugly CFI dwarf debuginfo annotations.
Conversion to C will reintroduce many of them - but meanwhile
they are only getting in the way, and the upstream kernel does
not rely on them (Ingo Molnar)
- NOP handling refinements. (Borislav Petkov)
* x86/mm changes:
- Big PAT and MTRR rework: making the code more robust and
preparing to phase out exposing direct MTRR interfaces to drivers -
in favor of using PAT driven interfaces (Toshi Kani, Luis R
Rodriguez, Borislav Petkov)
- New ioremap_wt()/set_memory_wt() interfaces to support
Write-Through cached memory mappings. This is especially
important for good performance on NVDIMM hardware (Toshi Kani)
* x86/ras changes:
- Add support for deferred errors on AMD (Aravind Gopalakrishnan)
This is an important RAS feature which adds hardware support for
poisoned data. That means roughly that the hardware marks data
which it has detected as corrupted but wasn't able to correct, as
poisoned data and raises an APIC interrupt to signal that in the
form of a deferred error. It is the OS's responsibility then to
take proper recovery action and thus prolonge system lifetime as
far as possible.
- Add support for Intel "Local MCE"s: upcoming CPUs will support
CPU-local MCE interrupts, as opposed to the traditional system-
wide broadcasted MCE interrupts (Ashok Raj)
- Misc cleanups (Borislav Petkov)
* x86/platform changes:
- Intel Atom SoC updates
... and lots of other cleanups, fixlets and other changes - see the
shortlog and the Git log for details"
* 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (222 commits)
x86/hpet: Use proper hpet device number for MSI allocation
x86/hpet: Check for irq==0 when allocating hpet MSI interrupts
x86/mm/pat, drivers/infiniband/ipath: Use arch_phys_wc_add() and require PAT disabled
x86/mm/pat, drivers/media/ivtv: Use arch_phys_wc_add() and require PAT disabled
x86/platform/intel/baytrail: Add comments about why we disabled HPET on Baytrail
genirq: Prevent crash in irq_move_irq()
genirq: Enhance irq_data_to_desc() to support hierarchy irqdomain
iommu, x86: Properly handle posted interrupts for IOMMU hotplug
iommu, x86: Provide irq_remapping_cap() interface
iommu, x86: Setup Posted-Interrupts capability for Intel iommu
iommu, x86: Add cap_pi_support() to detect VT-d PI capability
iommu, x86: Avoid migrating VT-d posted interrupts
iommu, x86: Save the mode (posted or remapped) of an IRTE
iommu, x86: Implement irq_set_vcpu_affinity for intel_ir_chip
iommu: dmar: Provide helper to copy shared irte fields
iommu: dmar: Extend struct irte for VT-d Posted-Interrupts
iommu: Add new member capability to struct irq_remap_ops
x86/asm/entry/64: Disentangle error_entry/exit gsbase/ebx/usermode code
x86/asm/entry/32: Shorten __audit_syscall_entry() args preparation
x86/asm/entry/32: Explain reloading of registers after __audit_syscall_entry()
...
This commit is contained in:
Linus Torvalds
@@ -4,7 +4,7 @@ include ../lib.mk
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.PHONY: all all_32 all_64 warn_32bit_failure clean
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TARGETS_C_BOTHBITS := sigreturn single_step_syscall
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TARGETS_C_BOTHBITS := sigreturn single_step_syscall sysret_ss_attrs
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TARGETS_C_32BIT_ONLY := entry_from_vm86
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TARGETS_C_32BIT_ALL := $(TARGETS_C_BOTHBITS) $(TARGETS_C_32BIT_ONLY)
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@@ -57,3 +57,6 @@ warn_32bit_failure:
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echo " yum install glibc-devel.*i686"; \
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exit 0;
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endif
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# Some tests have additional dependencies.
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sysret_ss_attrs_64: thunks.S
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112
tools/testing/selftests/x86/sysret_ss_attrs.c
Normal file
112
tools/testing/selftests/x86/sysret_ss_attrs.c
Normal file
@@ -0,0 +1,112 @@
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/*
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* sysret_ss_attrs.c - test that syscalls return valid hidden SS attributes
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* Copyright (c) 2015 Andrew Lutomirski
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* On AMD CPUs, SYSRET can return with a valid SS descriptor with with
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* the hidden attributes set to an unusable state. Make sure the kernel
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* doesn't let this happen.
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*/
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#define _GNU_SOURCE
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#include <stdlib.h>
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#include <unistd.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <err.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <pthread.h>
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static void *threadproc(void *ctx)
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{
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/*
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* Do our best to cause sleeps on this CPU to exit the kernel and
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* re-enter with SS = 0.
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*/
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while (true)
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;
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return NULL;
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}
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#ifdef __x86_64__
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extern unsigned long call32_from_64(void *stack, void (*function)(void));
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asm (".pushsection .text\n\t"
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".code32\n\t"
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"test_ss:\n\t"
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"pushl $0\n\t"
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"popl %eax\n\t"
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"ret\n\t"
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".code64");
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extern void test_ss(void);
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#endif
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int main()
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{
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/*
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* Start a busy-looping thread on the same CPU we're on.
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* For simplicity, just stick everything to CPU 0. This will
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* fail in some containers, but that's probably okay.
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*/
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cpu_set_t cpuset;
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CPU_ZERO(&cpuset);
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CPU_SET(0, &cpuset);
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if (sched_setaffinity(0, sizeof(cpuset), &cpuset) != 0)
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printf("[WARN]\tsched_setaffinity failed\n");
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pthread_t thread;
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if (pthread_create(&thread, 0, threadproc, 0) != 0)
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err(1, "pthread_create");
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#ifdef __x86_64__
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unsigned char *stack32 = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
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MAP_32BIT | MAP_ANONYMOUS | MAP_PRIVATE,
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-1, 0);
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if (stack32 == MAP_FAILED)
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err(1, "mmap");
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#endif
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printf("[RUN]\tSyscalls followed by SS validation\n");
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for (int i = 0; i < 1000; i++) {
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/*
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* Go to sleep and return using sysret (if we're 64-bit
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* or we're 32-bit on AMD on a 64-bit kernel). On AMD CPUs,
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* SYSRET doesn't fix up the cached SS descriptor, so the
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* kernel needs some kind of workaround to make sure that we
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* end the system call with a valid stack segment. This
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* can be a confusing failure because the SS *selector*
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* is the same regardless.
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*/
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usleep(2);
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#ifdef __x86_64__
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/*
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* On 32-bit, just doing a syscall through glibc is enough
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* to cause a crash if our cached SS descriptor is invalid.
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* On 64-bit, it's not, so try extra hard.
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*/
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call32_from_64(stack32 + 4088, test_ss);
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#endif
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}
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printf("[OK]\tWe survived\n");
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#ifdef __x86_64__
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munmap(stack32, 4096);
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#endif
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return 0;
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}
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67
tools/testing/selftests/x86/thunks.S
Normal file
67
tools/testing/selftests/x86/thunks.S
Normal file
@@ -0,0 +1,67 @@
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/*
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* thunks.S - assembly helpers for mixed-bitness code
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* Copyright (c) 2015 Andrew Lutomirski
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* These are little helpers that make it easier to switch bitness on
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* the fly.
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*/
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.text
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.global call32_from_64
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.type call32_from_64, @function
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call32_from_64:
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// rdi: stack to use
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// esi: function to call
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// Save registers
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pushq %rbx
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pushq %rbp
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pushq %r12
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pushq %r13
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pushq %r14
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pushq %r15
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pushfq
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// Switch stacks
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mov %rsp,(%rdi)
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mov %rdi,%rsp
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// Switch to compatibility mode
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pushq $0x23 /* USER32_CS */
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pushq $1f
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lretq
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1:
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.code32
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// Call the function
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call *%esi
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// Switch back to long mode
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jmp $0x33,$1f
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.code64
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1:
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// Restore the stack
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mov (%rsp),%rsp
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// Restore registers
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popfq
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popq %r15
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popq %r14
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popq %r13
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popq %r12
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popq %rbp
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popq %rbx
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ret
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.size call32_from_64, .-call32_from_64
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Reference in New Issue
Block a user