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clk: meson: split divider and gate part of mpll

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The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
2018-02-12 15:58:43 +01:00
committed by Neil Armstrong
parent 722825dcd5
commit d610b54f77
8 changed files with 233 additions and 154 deletions
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6
drivers/clk/meson/meson8b.h
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@@ -69,7 +69,11 @@
* will remain defined here.
*/
#define CLK_NR_CLKS 96
#define CLKID_MPLL0_DIV 96
#define CLKID_MPLL1_DIV 97
#define CLKID_MPLL2_DIV 98
#define CLK_NR_CLKS 99
/*
* include the CLKID and RESETID that have