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drm/omap: omap_display_timings: rename vsw to vsync_len

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In preparation to move the stack to use the generic videmode struct for
display timing information rename the vsw member to vsync_len.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Peter Ujfalusi
2016-09-22 14:06:51 +03:00
committed by Tomi Valkeinen
parent a85f4a8078
commit d5bcf0aa3f
18 changed files with 31 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/omapdrm/dss/dispc.c
View File

@@ -2869,7 +2869,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
} else {
int wbdelay;
wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
wbdelay = min(mgr_timings->vfp + mgr_timings->vsync_len +
mgr_timings->vbp, 255);
/* WBDELAYCOUNT */
@@ -3133,7 +3133,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
if (!_dispc_lcd_timings_ok(timings->hsync_len,
timings->hfront_porch, timings->hback_porch,
timings->vsw, timings->vfp, timings->vbp))
timings->vsync_len, timings->vfp, timings->vbp))
return false;
}
@@ -3270,12 +3270,12 @@ void dispc_mgr_set_timings(enum omap_channel channel,
if (dss_mgr_is_lcd(channel)) {
_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch,
t.hback_porch, t.vsw, t.vfp, t.vbp,
t.hback_porch, t.vsync_len, t.vfp, t.vbp,
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
ytot = t.vactive + t.vfp + t.vsw + t.vbp;
ytot = t.vactive + t.vfp + t.vsync_len + t.vbp;
ht = timings->pixelclock / xtot;
vt = timings->pixelclock / xtot / ytot;
@@ -3283,7 +3283,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
DSSDBG("pck %u\n", timings->pixelclock);
DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
t.hsync_len, t.hfront_porch, t.hback_porch,
t.vsw, t.vfp, t.vbp);
t.vsync_len, t.vfp, t.vbp);
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
@@ -4227,7 +4227,7 @@ static const struct dispc_errata_i734_data {
.hactive = 8, .vactive = 1,
.pixelclock = 16000000,
.hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
.vsw = 1, .vfp = 1, .vbp = 1,
.vsync_len = 1, .vfp = 1, .vbp = 1,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.interlace = false,

4
drivers/gpu/drm/omapdrm/dss/display.c
View File

@@ -231,7 +231,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
ovt->vactive = vm->vactive;
ovt->vbp = vm->vback_porch;
ovt->vfp = vm->vfront_porch;
ovt->vsw = vm->vsync_len;
ovt->vsync_len = vm->vsync_len;
ovt->vsync_level = vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
@@ -264,7 +264,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
vm->vactive = ovt->vactive;
vm->vback_porch = ovt->vbp;
vm->vfront_porch = ovt->vfp;
vm->vsync_len = ovt->vsw;
vm->vsync_len = ovt->vsync_len;
if (ovt->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;

4
drivers/gpu/drm/omapdrm/dss/dsi.c
View File

@@ -4423,7 +4423,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
t->pixelclock = pck;
t->hactive = ctx->config->timings->hactive;
t->vactive = ctx->config->timings->vactive;
t->hsync_len = t->hfront_porch = t->hback_porch = t->vsw = 1;
t->hsync_len = t->hfront_porch = t->hback_porch = t->vsync_len = 1;
t->vfp = t->vbp = 0;
return true;
@@ -4634,7 +4634,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
dsi_vm->hact = xres;
dsi_vm->hfp = hfp;
dsi_vm->vsa = req_vm->vsw;
dsi_vm->vsa = req_vm->vsync_len;
dsi_vm->vbp = req_vm->vbp;
dsi_vm->vact = req_vm->vactive;
dsi_vm->vfp = req_vm->vfp;

6
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
View File

@@ -299,7 +299,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
video_cfg->hblank = cfg->timings.hfront_porch +
cfg->timings.hback_porch + cfg->timings.hsync_len;
video_cfg->vblank_osc = 0;
video_cfg->vblank = cfg->timings.vsw +
video_cfg->vblank = cfg->timings.vsync_len +
cfg->timings.vfp + cfg->timings.vbp;
video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
@@ -311,7 +311,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
video_cfg->v_fc_config.timings.vactive /= 2;
video_cfg->vblank /= 2;
video_cfg->v_fc_config.timings.vfp /= 2;
video_cfg->v_fc_config.timings.vsw /= 2;
video_cfg->v_fc_config.timings.vsync_len /= 2;
video_cfg->v_fc_config.timings.vbp /= 2;
}
@@ -383,7 +383,7 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
/* set vertical sync pulse width */
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
cfg->v_fc_config.timings.vsw, 5, 0);
cfg->v_fc_config.timings.vsync_len, 5, 0);
/* select DVI mode */
REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,

6
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
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@@ -188,7 +188,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
timing_v |= FLD_VAL(timings->vbp, 31, 20);
timing_v |= FLD_VAL(timings->vfp, 19, 8);
timing_v |= FLD_VAL(timings->vsw, 7, 0);
timing_v |= FLD_VAL(timings->vsync_len, 7, 0);
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
}
@@ -206,7 +206,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
timings->hsync_len = param->timings.hsync_len;
timings->vbp = param->timings.vbp;
timings->vfp = param->timings.vfp;
timings->vsw = param->timings.vsw;
timings->vsync_len = param->timings.vsync_len;
timings->vsync_level = param->timings.vsync_level;
timings->hsync_level = param->timings.hsync_level;
@@ -217,7 +217,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
video_fmt->y_res /= 2;
timings->vbp /= 2;
timings->vfp /= 2;
timings->vsw /= 2;
timings->vsync_len /= 2;
}
if (param->timings.double_pixel) {

2
drivers/gpu/drm/omapdrm/dss/omapdss.h
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@@ -313,7 +313,7 @@ struct omap_video_timings {
/* Unit: pixel clocks */
u16 hback_porch; /* Horizontal back porch */
/* Unit: line clocks */
u16 vsw; /* Vertical synchronization pulse width */
u16 vsync_len; /* Vertical synchronization pulse width */
/* Unit: line clocks */
u16 vfp; /* Vertical front porch */
/* Unit: line clocks */

2
drivers/gpu/drm/omapdrm/dss/rfbi.c
View File

@@ -861,7 +861,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
rfbi.timings.hsync_len = 1;
rfbi.timings.hfront_porch = 1;
rfbi.timings.hback_porch = 1;
rfbi.timings.vsw = 1;
rfbi.timings.vsync_len = 1;
rfbi.timings.vfp = 0;
rfbi.timings.vbp = 0;

4
drivers/gpu/drm/omapdrm/dss/venc.c
View File

@@ -269,7 +269,7 @@ const struct omap_video_timings omap_dss_pal_timings = {
.hsync_len = 64,
.hfront_porch = 12,
.hback_porch = 68,
.vsw = 5,
.vsync_len = 5,
.vfp = 5,
.vbp = 41,
@@ -290,7 +290,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
.hsync_len = 64,
.hfront_porch = 16,
.hback_porch = 58,
.vsw = 6,
.vsync_len = 6,
.vfp = 6,
.vbp = 31,