drm/radeon: take ownership of pipe initialization
Take ownership of pipe initialization away from KFD. Note that hpd_eop_gpu_addr was already large enough to accomodate all pipes. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher

parent
dc102c436f
commit
d59095f7dd
@@ -4580,23 +4580,24 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
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/* init the pipes */
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mutex_lock(&rdev->srbm_mutex);
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eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr;
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for (i = 0; i < rdev->mec.num_pipe; ++i) {
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cik_srbm_select(rdev, 0, i, 0, 0);
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cik_srbm_select(rdev, 0, 0, 0, 0);
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eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;
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/* write the EOP addr */
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WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
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WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
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/* write the EOP addr */
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WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
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WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
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/* set the VMID assigned */
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WREG32(CP_HPD_EOP_VMID, 0);
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/* set the VMID assigned */
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WREG32(CP_HPD_EOP_VMID, 0);
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/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
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tmp = RREG32(CP_HPD_EOP_CONTROL);
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tmp &= ~EOP_SIZE_MASK;
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tmp |= order_base_2(MEC_HPD_SIZE / 8);
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WREG32(CP_HPD_EOP_CONTROL, tmp);
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/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
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tmp = RREG32(CP_HPD_EOP_CONTROL);
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tmp &= ~EOP_SIZE_MASK;
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tmp |= order_base_2(MEC_HPD_SIZE / 8);
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WREG32(CP_HPD_EOP_CONTROL, tmp);
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}
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mutex_unlock(&rdev->srbm_mutex);
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/* init the queues. Just two for now. */
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