qed*: Utilize FW 8.37.2.0
This FW contains several fixes and features. RDMA - Several modifications and fixes for Memory Windows - drop vlan and tcp timestamp from mss calculation in driver for this FW - Fix SQ completion flow when local ack timeout is infinite - Modifications in t10dif support ETH - Fix aRFS for tunneled traffic without inner IP. - Fix chip configuration which may fail under heavy traffic conditions. - Support receiving any-VNI in VXLAN and GENEVE RX classification. iSCSI / FcoE - Fix iSCSI recovery flow - Drop vlan and tcp timestamp from mss calc for fw 8.37.2.0 Misc - Several registers (split registers) won't read correctly with ethtool -d Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com> Signed-off-by: Manish Rangankar <manish.rangankar@cavium.com> Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller

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95358a9553
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d52c89f120
@@ -109,8 +109,8 @@
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#define MAX_NUM_LL2_TX_STATS_COUNTERS 48
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#define FW_MAJOR_VERSION 8
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#define FW_MINOR_VERSION 33
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#define FW_REVISION_VERSION 11
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#define FW_MINOR_VERSION 37
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#define FW_REVISION_VERSION 2
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#define FW_ENGINEERING_VERSION 0
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/***********************/
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@@ -799,8 +799,8 @@ struct e4_mstorm_iscsi_task_ag_ctx {
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
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#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
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@@ -849,8 +849,8 @@ struct e4_ustorm_iscsi_task_ag_ctx {
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#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
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#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
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#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
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#define E4_USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
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#define E4_USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
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#define E4_USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
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#define E4_USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
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#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
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#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
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u8 flags1;
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@@ -65,8 +65,7 @@ enum qed_roce_qp_state {
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enum qed_rdma_tid_type {
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QED_RDMA_TID_REGISTERED_MR,
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QED_RDMA_TID_FMR,
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QED_RDMA_TID_MW_TYPE1,
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QED_RDMA_TID_MW_TYPE2A
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QED_RDMA_TID_MW
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};
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struct qed_rdma_events {
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@@ -280,7 +279,6 @@ struct qed_rdma_register_tid_in_params {
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bool dif_enabled;
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u64 dif_error_addr;
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u64 dif_runt_addr;
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};
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struct qed_rdma_create_cq_in_params {
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@@ -43,6 +43,7 @@
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#define ROCE_MAX_QPS (32 * 1024)
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#define ROCE_DCQCN_NP_MAX_QPS (64)
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#define ROCE_DCQCN_RP_MAX_QPS (64)
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#define ROCE_LKEY_MW_DIF_EN_BIT (28)
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/* Affiliated asynchronous events / errors enumeration */
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enum roce_async_events_type {
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