Merge branches 'x86/amd', 'x86/vt-d', 'arm/rockchip', 'arm/omap', 'arm/mediatek', 'arm/exynos', 'arm/renesas', 'arm/smmu' and 'core' into next
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@@ -1412,7 +1412,7 @@ static struct irq_chip its_irq_chip = {
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* This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
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*/
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#define IRQS_PER_CHUNK_SHIFT 5
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#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
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#define IRQS_PER_CHUNK (1UL << IRQS_PER_CHUNK_SHIFT)
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#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
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static unsigned long *lpi_bitmap;
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@@ -2119,11 +2119,10 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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/*
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* At least one bit of EventID is being used, hence a minimum
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* of two entries. No, the architecture doesn't let you
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* express an ITT with a single entry.
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* We allocate at least one chunk worth of LPIs bet device,
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* and thus that many ITEs. The device may require less though.
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*/
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nr_ites = max(2UL, roundup_pow_of_two(nvecs));
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nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs));
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sz = nr_ites * its->ite_size;
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sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
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itt = kzalloc(sz, GFP_KERNEL);
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@@ -2495,7 +2494,7 @@ static int its_vpe_set_affinity(struct irq_data *d,
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static void its_vpe_schedule(struct its_vpe *vpe)
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{
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void * __iomem vlpi_base = gic_data_rdist_vlpi_base();
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void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
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u64 val;
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/* Schedule the VPE */
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@@ -2527,7 +2526,7 @@ static void its_vpe_schedule(struct its_vpe *vpe)
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static void its_vpe_deschedule(struct its_vpe *vpe)
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{
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void * __iomem vlpi_base = gic_data_rdist_vlpi_base();
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void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
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u32 count = 1000000; /* 1s! */
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bool clean;
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u64 val;
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@@ -3314,6 +3313,8 @@ static int __init its_of_probe(struct device_node *node)
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for (np = of_find_matching_node(node, its_device_id); np;
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np = of_find_matching_node(np, its_device_id)) {
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if (!of_device_is_available(np))
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continue;
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if (!of_property_read_bool(np, "msi-controller")) {
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pr_warn("%pOF: no msi-controller property, ITS ignored\n",
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np);
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@@ -3450,7 +3451,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
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return -ENOMEM;
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}
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err = iort_register_domain_token(its_entry->translation_id, dom_handle);
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err = iort_register_domain_token(its_entry->translation_id, res.start,
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dom_handle);
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if (err) {
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pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
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&res.start, its_entry->translation_id);
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