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Merge tag 'mlx5-updates-2017-06-23' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

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Saeed Mahameed says:

====================
mlx5-updates-2017-06-23

This series provides some updates to the mlx5 core and netdevice drivers.

Three patches from Tariq, Introduces page reuse mechanism in non-Striding
RQ RX datapath, we allow the the RX descriptor to reuse its allocated page
as much as it could, until the page is fully consumed. RX page reuse
reduces the stress on page allocator and improves RX performance especially
with high speeds (100Gb/s).

Next four patches of the series from Or allows to offload tc flower matching
on ttl/hoplimit and header re-write of hoplimit.

The rest of  the series from Yotam and Or enhances mlx5 to support FW flashing
through the mlxfw module, in a similar manner done by the mlxsw driver.
Currently, only ethtool based flashing is implemented, where both Eth and IB ports
are supported.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2017-06-23 14:24:28 -04:00
parent 8f46d46715 137ffd15f7
commit d4d0249ae2
14 changed files with 630 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
include/linux/mlx5/device.h
View File

@@ -1094,6 +1094,9 @@ enum mlx5_mcam_feature_groups {
#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
#define MLX5_CAP_MCAM_REG(mdev, reg) \
MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)

3
include/linux/mlx5/driver.h
View File

@@ -131,6 +131,9 @@ enum {
MLX5_REG_MPCNT = 0x9051,
MLX5_REG_MTPPS = 0x9053,
MLX5_REG_MTPPSE = 0x9054,
MLX5_REG_MCQI = 0x9061,
MLX5_REG_MCC = 0x9062,
MLX5_REG_MCDA = 0x9063,
MLX5_REG_MCAM = 0x907f,
};

103
include/linux/mlx5/mlx5_ifc.h
View File

@@ -243,7 +243,7 @@ struct mlx5_ifc_flow_table_fields_supported_bits {
u8 outer_first_prio[0x1];
u8 outer_first_cfi[0x1];
u8 outer_first_vid[0x1];
u8 reserved_at_7[0x1];
u8 outer_ipv4_ttl[0x1];
u8 outer_second_prio[0x1];
u8 outer_second_cfi[0x1];
u8 outer_second_vid[0x1];
@@ -380,7 +380,8 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
u8 tcp_sport[0x10];
u8 tcp_dport[0x10];
u8 reserved_at_c0[0x20];
u8 reserved_at_c0[0x18];
u8 ttl_hoplimit[0x8];
u8 udp_sport[0x10];
u8 udp_dport[0x10];
@@ -823,7 +824,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 cc_modify_allowed[0x1];
u8 start_pad[0x1];
u8 cache_line_128byte[0x1];
u8 reserved_at_163[0xb];
u8 reserved_at_165[0xb];
u8 gid_table_size[0x10];
u8 out_of_seq_cnt[0x1];
@@ -4619,6 +4620,7 @@ enum {
MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
};
struct mlx5_ifc_alloc_modify_header_context_out_bits {
@@ -7743,6 +7745,18 @@ struct mlx5_ifc_mcam_enhanced_features_bits {
u8 pcie_performance_group[0x1];
};
struct mlx5_ifc_mcam_access_reg_bits {
u8 reserved_at_0[0x1c];
u8 mcda[0x1];
u8 mcc[0x1];
u8 mcqi[0x1];
u8 reserved_at_1f[0x1];
u8 regs_95_to_64[0x20];
u8 regs_63_to_32[0x20];
u8 regs_31_to_0[0x20];
};
struct mlx5_ifc_mcam_reg_bits {
u8 reserved_at_0[0x8];
u8 feature_group[0x8];
@@ -7752,6 +7766,7 @@ struct mlx5_ifc_mcam_reg_bits {
u8 reserved_at_20[0x20];
union {
struct mlx5_ifc_mcam_access_reg_bits access_regs;
u8 reserved_at_0[0x80];
} mng_access_reg_cap_mask;
@@ -8163,6 +8178,85 @@ struct mlx5_ifc_mtppse_reg_bits {
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_mcqi_cap_bits {
u8 supported_info_bitmask[0x20];
u8 component_size[0x20];
u8 max_component_size[0x20];
u8 log_mcda_word_size[0x4];
u8 reserved_at_64[0xc];
u8 mcda_max_write_size[0x10];
u8 rd_en[0x1];
u8 reserved_at_81[0x1];
u8 match_chip_id[0x1];
u8 match_psid[0x1];
u8 check_user_timestamp[0x1];
u8 match_base_guid_mac[0x1];
u8 reserved_at_86[0x1a];
};
struct mlx5_ifc_mcqi_reg_bits {
u8 read_pending_component[0x1];
u8 reserved_at_1[0xf];
u8 component_index[0x10];
u8 reserved_at_20[0x20];
u8 reserved_at_40[0x1b];
u8 info_type[0x5];
u8 info_size[0x20];
u8 offset[0x20];
u8 reserved_at_a0[0x10];
u8 data_size[0x10];
u8 data[0][0x20];
};
struct mlx5_ifc_mcc_reg_bits {
u8 reserved_at_0[0x4];
u8 time_elapsed_since_last_cmd[0xc];
u8 reserved_at_10[0x8];
u8 instruction[0x8];
u8 reserved_at_20[0x10];
u8 component_index[0x10];
u8 reserved_at_40[0x8];
u8 update_handle[0x18];
u8 handle_owner_type[0x4];
u8 handle_owner_host_id[0x4];
u8 reserved_at_68[0x1];
u8 control_progress[0x7];
u8 error_code[0x8];
u8 reserved_at_78[0x4];
u8 control_state[0x4];
u8 component_size[0x20];
u8 reserved_at_a0[0x60];
};
struct mlx5_ifc_mcda_reg_bits {
u8 reserved_at_0[0x8];
u8 update_handle[0x18];
u8 offset[0x20];
u8 reserved_at_40[0x10];
u8 size[0x10];
u8 reserved_at_60[0x20];
u8 data[0][0x20];
};
union mlx5_ifc_ports_control_registers_document_bits {
struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -8212,6 +8306,9 @@ union mlx5_ifc_ports_control_registers_document_bits {
struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
struct mlx5_ifc_mcc_reg_bits mcc_reg;
struct mlx5_ifc_mcda_reg_bits mcda_reg;
u8 reserved_at_0[0x60e0];
};