MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs
This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
committed by
Ralf Baechle
Ralf Baechle
parent
94bb0c1ab2
commit
d4a67d9dc8
187
arch/mips/ath79/irq.c
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187
arch/mips/ath79/irq.c
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/*
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* Atheros AR71xx/AR724x/AR913x specific interrupt handling
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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static unsigned int ath79_ip2_flush_reg;
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static unsigned int ath79_ip3_flush_reg;
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ath79_reset_base;
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u32 pending;
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pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (pending & MISC_INT_UART)
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generic_handle_irq(ATH79_MISC_IRQ_UART);
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else if (pending & MISC_INT_DMA)
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generic_handle_irq(ATH79_MISC_IRQ_DMA);
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else if (pending & MISC_INT_PERFC)
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generic_handle_irq(ATH79_MISC_IRQ_PERFC);
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else if (pending & MISC_INT_TIMER)
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generic_handle_irq(ATH79_MISC_IRQ_TIMER);
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else if (pending & MISC_INT_OHCI)
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generic_handle_irq(ATH79_MISC_IRQ_OHCI);
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else if (pending & MISC_INT_ERROR)
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generic_handle_irq(ATH79_MISC_IRQ_ERROR);
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else if (pending & MISC_INT_GPIO)
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generic_handle_irq(ATH79_MISC_IRQ_GPIO);
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else if (pending & MISC_INT_WDOG)
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generic_handle_irq(ATH79_MISC_IRQ_WDOG);
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else
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spurious_interrupt();
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}
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static void ar71xx_misc_irq_unmask(unsigned int irq)
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{
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void __iomem *base = ath79_reset_base;
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u32 t;
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irq -= ATH79_MISC_IRQ_BASE;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(unsigned int irq)
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{
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void __iomem *base = ath79_reset_base;
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u32 t;
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irq -= ATH79_MISC_IRQ_BASE;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(unsigned int irq)
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{
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void __iomem *base = ath79_reset_base;
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u32 t;
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irq -= ATH79_MISC_IRQ_BASE;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ath79_misc_irq_chip = {
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.name = "MISC",
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.unmask = ar71xx_misc_irq_unmask,
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.mask = ar71xx_misc_irq_mask,
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};
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static void __init ath79_misc_irq_init(void)
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{
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void __iomem *base = ath79_reset_base;
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int i;
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
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else if (soc_is_ar724x())
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ath79_misc_irq_chip.ack = ar724x_misc_irq_ack;
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else
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BUG();
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for (i = ATH79_MISC_IRQ_BASE;
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i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
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handle_level_irq);
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}
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set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(ATH79_CPU_IRQ_TIMER);
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else if (pending & STATUSF_IP2) {
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ath79_ddr_wb_flush(ath79_ip2_flush_reg);
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do_IRQ(ATH79_CPU_IRQ_IP2);
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}
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else if (pending & STATUSF_IP4)
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do_IRQ(ATH79_CPU_IRQ_GE0);
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else if (pending & STATUSF_IP5)
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do_IRQ(ATH79_CPU_IRQ_GE1);
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else if (pending & STATUSF_IP3) {
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ath79_ddr_wb_flush(ath79_ip3_flush_reg);
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do_IRQ(ATH79_CPU_IRQ_USB);
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}
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else if (pending & STATUSF_IP6)
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do_IRQ(ATH79_CPU_IRQ_MISC);
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else
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spurious_interrupt();
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}
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void __init arch_init_irq(void)
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{
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if (soc_is_ar71xx()) {
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ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
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ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
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} else if (soc_is_ar724x()) {
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ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
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ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
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} else if (soc_is_ar913x()) {
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ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
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ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
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} else
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BUG();
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cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
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mips_cpu_irq_init();
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ath79_misc_irq_init();
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}
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