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Merge v5.6-rc5 into drm-next

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Requested my mripard for some misc patches that need this as a base.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2020-03-11 07:27:21 +10:00
parent 60347451dd 2c523b344d
commit d3bd37f587
895 changed files with 9621 additions and 7019 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
View File

@@ -255,13 +255,13 @@ static const struct dpu_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(RGB565,
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR565,
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, 0,
DPU_FETCH_LINEAR, 1),

58
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
View File

@@ -12,6 +12,7 @@
#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
#define HW_REV 0x0
#define HW_INTR_STATUS 0x0010
/* Max BW defined in KBps */
@@ -22,6 +23,17 @@ struct dpu_irq_controller {
struct irq_domain *domain;
};
struct dpu_hw_cfg {
u32 val;
u32 offset;
};
struct dpu_mdss_hw_init_handler {
u32 hw_rev;
u32 hw_reg_count;
struct dpu_hw_cfg* hw_cfg;
};
struct dpu_mdss {
struct msm_mdss base;
void __iomem *mmio;
@@ -32,6 +44,44 @@ struct dpu_mdss {
u32 num_paths;
};
static struct dpu_hw_cfg hw_cfg[] = {
{
/* UBWC global settings */
.val = 0x1E,
.offset = 0x144,
}
};
static struct dpu_mdss_hw_init_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_620,
.hw_reg_count = ARRAY_SIZE(hw_cfg),
.hw_cfg = hw_cfg
},
};
static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev)
{
int i;
u32 count = 0;
struct dpu_hw_cfg *hw_cfg = NULL;
for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
if (cfg_handler[i].hw_rev == hw_rev) {
hw_cfg = cfg_handler[i].hw_cfg;
count = cfg_handler[i].hw_reg_count;
break;
}
}
for (i = 0; i < count; i++ ) {
writel_relaxed(hw_cfg->val,
dpu_mdss->mmio + hw_cfg->offset);
hw_cfg++;
}
return;
}
static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
struct dpu_mdss *dpu_mdss)
{
@@ -174,12 +224,18 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = &dpu_mdss->mp;
int ret;
u32 mdss_rev;
dpu_mdss_icc_request_bw(mdss);
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (ret)
if (ret) {
DPU_ERROR("clock enable failed, ret:%d\n", ret);
return ret;
}
mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV);
dpu_mdss_hw_init(dpu_mdss, mdss_rev);
return ret;
}

4
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
View File

@@ -1191,8 +1191,8 @@ static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
msecs_to_jiffies(50));
if (ret == 0)
dev_warn(dev->dev, "pp done time out, lm=%d\n",
mdp5_cstate->pipeline.mixer->lm);
dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
mdp5_cstate->pipeline.mixer->lm);
}
static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)