Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Misc driver updates for platforms, many of them power related.
- Rockchip adds power domain support for rk3066 and rk3188
- Amlogic adds a power measurement driver
- Allwinner adds SRAM support for three platforms (F1C100, H5, A64
C1)
- Wakeup and ti-sysc (platform bus) fixes for OMAP/DRA7
- Broadcom fixes suspend/resume with Thumb2 kernels, and improves
stability of a handful of firmware/platform interfaces
- PXA completes their conversion to dmaengine framework
- Renesas does a bunch of PM cleanups across many platforms
- Tegra adds support for suspend/resume on T186/T194, which includes
some driver cleanups and addition of wake events
- Tegra also adds a driver for memory controller (EMC) on Tegra2
- i.MX tweaks power domain bindings, and adds support for i.MX8MQ in
GPC
- Atmel adds identifiers and LPDDR2 support for a new SoC, SAM9X60
and misc cleanups across several platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits)
ARM: at91: add support in soc driver for new SAM9X60
ARM: at91: add support in soc driver for LPDDR2 SiP
memory: omap-gpmc: Use of_node_name_eq for node name comparisons
bus: ti-sysc: Check for no-reset and no-idle flags at the child level
ARM: OMAP2+: Check also the first dts child for hwmod flags
soc: amlogic: meson-clk-measure: Add missing REGMAP_MMIO dependency
soc: imx: gpc: Increase GPC_CLK_MAX to 7
soc: renesas: rcar-sysc: Fix power domain control after system resume
soc: renesas: rcar-sysc: Merge PM Domain registration and linking
soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers
soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B}
dt-bindings: sram: sunxi: Add compatible for the A64 SRAM C1
dt-bindings: sram: sunxi: Add bindings for the H5 with SRAM C1
dt-bindings: sram: Add Allwinner suniv F1C100s
soc: sunxi: sram: Add support for the H5 SoC system control
soc: sunxi: sram: Enable EMAC clock access for H3 variant
soc: imx: gpcv2: add support for i.MX8MQ SoC
soc: imx: gpcv2: move register access table to domain data
soc: imx: gpcv2: prefix i.MX7 specific defines
dmaengine: pxa: make the filter function internal
...
这个提交包含在：
Linus Torvalds
@@ -6,6 +6,16 @@ config TEGRA_MC
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This driver supports the Memory Controller (MC) hardware found on
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NVIDIA Tegra SoCs.
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config TEGRA20_EMC
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bool "NVIDIA Tegra20 External Memory Controller driver"
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default y
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depends on ARCH_TEGRA_2x_SOC
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help
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This driver is for the External Memory Controller (EMC) found on
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Tegra20 chips. The EMC controls the external DRAM on the board.
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This driver is required to change memory timings / clock rate for
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external memory.
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config TEGRA124_EMC
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bool "NVIDIA Tegra124 External Memory Controller driver"
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default y
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@@ -10,5 +10,6 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
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obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
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591
drivers/memory/tegra/tegra20-emc.c
普通文件
591
drivers/memory/tegra/tegra20-emc.c
普通文件
@@ -0,0 +1,591 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Tegra20 External Memory Controller driver
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*
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* Author: Dmitry Osipenko <digetx@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/sort.h>
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#include <linux/types.h>
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#include <soc/tegra/fuse.h>
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#define EMC_INTSTATUS 0x000
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#define EMC_INTMASK 0x004
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#define EMC_TIMING_CONTROL 0x028
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#define EMC_RC 0x02c
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#define EMC_RFC 0x030
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#define EMC_RAS 0x034
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#define EMC_RP 0x038
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#define EMC_R2W 0x03c
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#define EMC_W2R 0x040
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#define EMC_R2P 0x044
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#define EMC_W2P 0x048
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#define EMC_RD_RCD 0x04c
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#define EMC_WR_RCD 0x050
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#define EMC_RRD 0x054
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#define EMC_REXT 0x058
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#define EMC_WDV 0x05c
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#define EMC_QUSE 0x060
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#define EMC_QRST 0x064
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#define EMC_QSAFE 0x068
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#define EMC_RDV 0x06c
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#define EMC_REFRESH 0x070
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#define EMC_BURST_REFRESH_NUM 0x074
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#define EMC_PDEX2WR 0x078
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#define EMC_PDEX2RD 0x07c
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#define EMC_PCHG2PDEN 0x080
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#define EMC_ACT2PDEN 0x084
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#define EMC_AR2PDEN 0x088
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#define EMC_RW2PDEN 0x08c
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#define EMC_TXSR 0x090
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#define EMC_TCKE 0x094
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#define EMC_TFAW 0x098
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#define EMC_TRPAB 0x09c
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#define EMC_TCLKSTABLE 0x0a0
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#define EMC_TCLKSTOP 0x0a4
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#define EMC_TREFBW 0x0a8
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#define EMC_QUSE_EXTRA 0x0ac
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#define EMC_ODT_WRITE 0x0b0
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#define EMC_ODT_READ 0x0b4
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#define EMC_FBIO_CFG5 0x104
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#define EMC_FBIO_CFG6 0x114
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#define EMC_AUTO_CAL_INTERVAL 0x2a8
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#define EMC_CFG_2 0x2b8
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#define EMC_CFG_DIG_DLL 0x2bc
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#define EMC_DLL_XFORM_DQS 0x2c0
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#define EMC_DLL_XFORM_QUSE 0x2c4
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#define EMC_ZCAL_REF_CNT 0x2e0
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#define EMC_ZCAL_WAIT_CNT 0x2e4
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#define EMC_CFG_CLKTRIM_0 0x2d0
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#define EMC_CFG_CLKTRIM_1 0x2d4
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#define EMC_CFG_CLKTRIM_2 0x2d8
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#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
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#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
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#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
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#define EMC_TIMING_UPDATE BIT(0)
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#define EMC_REFRESH_OVERFLOW_INT BIT(3)
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#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
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static const u16 emc_timing_registers[] = {
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EMC_RC,
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EMC_RFC,
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EMC_RAS,
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EMC_RP,
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EMC_R2W,
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EMC_W2R,
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EMC_R2P,
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EMC_W2P,
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EMC_RD_RCD,
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EMC_WR_RCD,
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EMC_RRD,
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EMC_REXT,
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EMC_WDV,
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EMC_QUSE,
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EMC_QRST,
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EMC_QSAFE,
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EMC_RDV,
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EMC_REFRESH,
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EMC_BURST_REFRESH_NUM,
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EMC_PDEX2WR,
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EMC_PDEX2RD,
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EMC_PCHG2PDEN,
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EMC_ACT2PDEN,
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EMC_AR2PDEN,
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EMC_RW2PDEN,
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EMC_TXSR,
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EMC_TCKE,
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EMC_TFAW,
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EMC_TRPAB,
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EMC_TCLKSTABLE,
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EMC_TCLKSTOP,
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EMC_TREFBW,
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EMC_QUSE_EXTRA,
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EMC_FBIO_CFG6,
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EMC_ODT_WRITE,
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EMC_ODT_READ,
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EMC_FBIO_CFG5,
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EMC_CFG_DIG_DLL,
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EMC_DLL_XFORM_DQS,
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EMC_DLL_XFORM_QUSE,
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EMC_ZCAL_REF_CNT,
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EMC_ZCAL_WAIT_CNT,
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EMC_AUTO_CAL_INTERVAL,
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EMC_CFG_CLKTRIM_0,
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EMC_CFG_CLKTRIM_1,
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EMC_CFG_CLKTRIM_2,
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};
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struct emc_timing {
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unsigned long rate;
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u32 data[ARRAY_SIZE(emc_timing_registers)];
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};
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struct tegra_emc {
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struct device *dev;
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struct completion clk_handshake_complete;
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struct notifier_block clk_nb;
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struct clk *backup_clk;
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struct clk *emc_mux;
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struct clk *pll_m;
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struct clk *clk;
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void __iomem *regs;
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struct emc_timing *timings;
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unsigned int num_timings;
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};
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static irqreturn_t tegra_emc_isr(int irq, void *data)
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{
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struct tegra_emc *emc = data;
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u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
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u32 status;
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status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
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if (!status)
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return IRQ_NONE;
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/* notify about EMC-CAR handshake completion */
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if (status & EMC_CLKCHANGE_COMPLETE_INT)
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complete(&emc->clk_handshake_complete);
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/* notify about HW problem */
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if (status & EMC_REFRESH_OVERFLOW_INT)
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dev_err_ratelimited(emc->dev,
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"refresh request overflow timeout\n");
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/* clear interrupts */
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writel_relaxed(status, emc->regs + EMC_INTSTATUS);
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return IRQ_HANDLED;
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}
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static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
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unsigned long rate)
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{
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struct emc_timing *timing = NULL;
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unsigned int i;
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for (i = 0; i < emc->num_timings; i++) {
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if (emc->timings[i].rate >= rate) {
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timing = &emc->timings[i];
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break;
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}
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}
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if (!timing) {
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dev_err(emc->dev, "no timing for rate %lu\n", rate);
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return NULL;
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}
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return timing;
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}
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static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
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{
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struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
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unsigned int i;
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if (!timing)
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return -EINVAL;
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dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
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__func__, timing->rate, rate);
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/* program shadow registers */
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for (i = 0; i < ARRAY_SIZE(timing->data); i++)
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writel_relaxed(timing->data[i],
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emc->regs + emc_timing_registers[i]);
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/* wait until programming has settled */
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readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
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reinit_completion(&emc->clk_handshake_complete);
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return 0;
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}
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static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
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{
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long timeout;
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dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
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if (flush) {
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/* manually initiate memory timing update */
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writel_relaxed(EMC_TIMING_UPDATE,
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emc->regs + EMC_TIMING_CONTROL);
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return 0;
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}
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timeout = wait_for_completion_timeout(&emc->clk_handshake_complete,
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usecs_to_jiffies(100));
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if (timeout == 0) {
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dev_err(emc->dev, "EMC-CAR handshake failed\n");
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return -EIO;
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} else if (timeout < 0) {
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dev_err(emc->dev, "failed to wait for EMC-CAR handshake: %ld\n",
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timeout);
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return timeout;
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}
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return 0;
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}
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static int tegra_emc_clk_change_notify(struct notifier_block *nb,
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unsigned long msg, void *data)
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{
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struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
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struct clk_notifier_data *cnd = data;
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int err;
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switch (msg) {
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case PRE_RATE_CHANGE:
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err = emc_prepare_timing_change(emc, cnd->new_rate);
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break;
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case ABORT_RATE_CHANGE:
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err = emc_prepare_timing_change(emc, cnd->old_rate);
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if (err)
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break;
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err = emc_complete_timing_change(emc, true);
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break;
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case POST_RATE_CHANGE:
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err = emc_complete_timing_change(emc, false);
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break;
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default:
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return NOTIFY_DONE;
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}
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return notifier_from_errno(err);
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}
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static int load_one_timing_from_dt(struct tegra_emc *emc,
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struct emc_timing *timing,
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struct device_node *node)
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{
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u32 rate;
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int err;
|
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|
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if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
|
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dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
|
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return -EINVAL;
|
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}
|
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|
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err = of_property_read_u32(node, "clock-frequency", &rate);
|
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if (err) {
|
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dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
|
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node, err);
|
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return err;
|
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}
|
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|
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err = of_property_read_u32_array(node, "nvidia,emc-registers",
|
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timing->data,
|
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ARRAY_SIZE(emc_timing_registers));
|
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if (err) {
|
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dev_err(emc->dev,
|
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"timing %pOF: failed to read emc timing data: %d\n",
|
||||
node, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* The EMC clock rate is twice the bus rate, and the bus rate is
|
||||
* measured in kHz.
|
||||
*/
|
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timing->rate = rate * 2 * 1000;
|
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|
||||
dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
|
||||
__func__, node, timing->rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cmp_timings(const void *_a, const void *_b)
|
||||
{
|
||||
const struct emc_timing *a = _a;
|
||||
const struct emc_timing *b = _b;
|
||||
|
||||
if (a->rate < b->rate)
|
||||
return -1;
|
||||
|
||||
if (a->rate > b->rate)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct device_node *child;
|
||||
struct emc_timing *timing;
|
||||
int child_count;
|
||||
int err;
|
||||
|
||||
child_count = of_get_child_count(node);
|
||||
if (!child_count) {
|
||||
dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
|
||||
GFP_KERNEL);
|
||||
if (!emc->timings)
|
||||
return -ENOMEM;
|
||||
|
||||
emc->num_timings = child_count;
|
||||
timing = emc->timings;
|
||||
|
||||
for_each_child_of_node(node, child) {
|
||||
err = load_one_timing_from_dt(emc, timing++, child);
|
||||
if (err) {
|
||||
of_node_put(child);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
|
||||
NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct device_node *
|
||||
tegra_emc_find_node_by_ram_code(struct device *dev)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 value, ram_code;
|
||||
int err;
|
||||
|
||||
if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
|
||||
return of_node_get(dev->of_node);
|
||||
|
||||
ram_code = tegra_read_ram_code();
|
||||
|
||||
for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
|
||||
np = of_find_node_by_name(np, "emc-tables")) {
|
||||
err = of_property_read_u32(np, "nvidia,ram-code", &value);
|
||||
if (err || value != ram_code) {
|
||||
of_node_put(np);
|
||||
continue;
|
||||
}
|
||||
|
||||
return np;
|
||||
}
|
||||
|
||||
dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
|
||||
ram_code);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int emc_setup_hw(struct tegra_emc *emc)
|
||||
{
|
||||
u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
|
||||
u32 emc_cfg;
|
||||
|
||||
emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
|
||||
|
||||
/*
|
||||
* Depending on a memory type, DRAM should enter either self-refresh
|
||||
* or power-down state on EMC clock change.
|
||||
*/
|
||||
if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
|
||||
!(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
|
||||
dev_err(emc->dev,
|
||||
"bootloader didn't specify DRAM auto-suspend mode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* enable EMC and CAR to handshake on PLL divider/source changes */
|
||||
emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
|
||||
writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
|
||||
|
||||
/* initialize interrupt */
|
||||
writel_relaxed(intmask, emc->regs + EMC_INTMASK);
|
||||
writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int emc_init(struct tegra_emc *emc, unsigned long rate)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = clk_set_parent(emc->emc_mux, emc->backup_clk);
|
||||
if (err) {
|
||||
dev_err(emc->dev,
|
||||
"failed to reparent to backup source: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_rate(emc->pll_m, rate);
|
||||
if (err) {
|
||||
dev_err(emc->dev,
|
||||
"failed to change pll_m rate: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_parent(emc->emc_mux, emc->pll_m);
|
||||
if (err) {
|
||||
dev_err(emc->dev,
|
||||
"failed to reparent to pll_m: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_rate(emc->clk, rate);
|
||||
if (err) {
|
||||
dev_err(emc->dev,
|
||||
"failed to change emc rate: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_emc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct tegra_emc *emc;
|
||||
struct resource *res;
|
||||
int irq, err;
|
||||
|
||||
/* driver has nothing to do in a case of memory timing absence */
|
||||
if (of_get_child_count(pdev->dev.of_node) == 0) {
|
||||
dev_info(&pdev->dev,
|
||||
"EMC device tree node doesn't have memory timings\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "interrupt not specified\n");
|
||||
dev_err(&pdev->dev, "please update your device tree\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
np = tegra_emc_find_node_by_ram_code(&pdev->dev);
|
||||
if (!np)
|
||||
return -EINVAL;
|
||||
|
||||
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
|
||||
if (!emc) {
|
||||
of_node_put(np);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
init_completion(&emc->clk_handshake_complete);
|
||||
emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
|
||||
emc->dev = &pdev->dev;
|
||||
|
||||
err = tegra_emc_load_timings_from_dt(emc, np);
|
||||
of_node_put(np);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
emc->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(emc->regs))
|
||||
return PTR_ERR(emc->regs);
|
||||
|
||||
err = emc_setup_hw(emc);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
|
||||
dev_name(&pdev->dev), emc);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
emc->clk = devm_clk_get(&pdev->dev, "emc");
|
||||
if (IS_ERR(emc->clk)) {
|
||||
err = PTR_ERR(emc->clk);
|
||||
dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
emc->pll_m = clk_get_sys(NULL, "pll_m");
|
||||
if (IS_ERR(emc->pll_m)) {
|
||||
err = PTR_ERR(emc->pll_m);
|
||||
dev_err(&pdev->dev, "failed to get pll_m clock: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
emc->backup_clk = clk_get_sys(NULL, "pll_p");
|
||||
if (IS_ERR(emc->backup_clk)) {
|
||||
err = PTR_ERR(emc->backup_clk);
|
||||
dev_err(&pdev->dev, "failed to get pll_p clock: %d\n", err);
|
||||
goto put_pll_m;
|
||||
}
|
||||
|
||||
emc->emc_mux = clk_get_parent(emc->clk);
|
||||
if (IS_ERR(emc->emc_mux)) {
|
||||
err = PTR_ERR(emc->emc_mux);
|
||||
dev_err(&pdev->dev, "failed to get emc_mux clock: %d\n", err);
|
||||
goto put_backup;
|
||||
}
|
||||
|
||||
err = clk_notifier_register(emc->clk, &emc->clk_nb);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
|
||||
err);
|
||||
goto put_backup;
|
||||
}
|
||||
|
||||
/* set DRAM clock rate to maximum */
|
||||
err = emc_init(emc, emc->timings[emc->num_timings - 1].rate);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to initialize EMC clock rate: %d\n",
|
||||
err);
|
||||
goto unreg_notifier;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
unreg_notifier:
|
||||
clk_notifier_unregister(emc->clk, &emc->clk_nb);
|
||||
put_backup:
|
||||
clk_put(emc->backup_clk);
|
||||
put_pll_m:
|
||||
clk_put(emc->pll_m);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra_emc_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-emc", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver tegra_emc_driver = {
|
||||
.probe = tegra_emc_probe,
|
||||
.driver = {
|
||||
.name = "tegra20-emc",
|
||||
.of_match_table = tegra_emc_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init tegra_emc_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_emc_driver);
|
||||
}
|
||||
subsys_initcall(tegra_emc_init);
|
||||
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