tty: Blackin CTS/RTS
Both software emulated and hardware based CTS and RTS are enabled in serial driver. The CTS RTS PIN connection on BF548 UART port is defined as a modem device not as a host device. In order to test it under Linux, please nake a cross UART cable to exchange CTS and RTS signal. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:

کامیت شده توسط
Linus Torvalds

والد
6f95570e40
کامیت
d307d36ade
@@ -53,9 +53,9 @@
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#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
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#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
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#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
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#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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@@ -87,6 +87,7 @@
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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unsigned int lsr;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC00400,
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IRQ_UART0_RX,
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IRQ_UART0_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC02000,
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IRQ_UART1_RX,
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IRQ_UART1_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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@@ -53,9 +53,9 @@
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#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
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#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
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#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
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#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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@@ -87,6 +87,7 @@
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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unsigned int lsr;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC00400,
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IRQ_UART0_RX,
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IRQ_UART0_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC02000,
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IRQ_UART1_RX,
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IRQ_UART1_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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@@ -53,9 +53,9 @@
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#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
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#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
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#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
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#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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@@ -74,6 +74,7 @@
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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unsigned int lsr;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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@@ -116,6 +117,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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@@ -130,6 +132,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC00400,
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IRQ_UART_RX,
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IRQ_UART_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART_TX,
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CH_UART_RX,
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@@ -53,9 +53,9 @@
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#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
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#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
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#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
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#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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@@ -87,6 +87,7 @@
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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unsigned int lsr;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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@@ -124,6 +125,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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@@ -139,6 +141,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC00400,
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IRQ_UART0_RX,
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IRQ_UART0_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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@@ -153,6 +156,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC02000,
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IRQ_UART1_RX,
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IRQ_UART1_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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@@ -53,9 +53,9 @@
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#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
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#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
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#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
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#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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@@ -87,6 +87,7 @@
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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unsigned int lsr;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC00400,
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IRQ_UART0_RX,
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IRQ_UART0_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC02000,
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IRQ_UART1_RX,
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IRQ_UART1_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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@@ -46,41 +46,27 @@
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#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
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#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
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#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
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#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
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#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
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#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
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#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
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#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
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#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
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#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
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#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
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#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
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#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
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#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
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#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
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#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
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#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
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#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
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#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
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#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
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#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS)
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# define CONFIG_SERIAL_BFIN_CTSRTS
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# ifndef CONFIG_UART0_CTS_PIN
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# define CONFIG_UART0_CTS_PIN -1
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# endif
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# ifndef CONFIG_UART0_RTS_PIN
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# define CONFIG_UART0_RTS_PIN -1
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# endif
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# ifndef CONFIG_UART2_CTS_PIN
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# define CONFIG_UART2_CTS_PIN -1
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# endif
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# ifndef CONFIG_UART2_RTS_PIN
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# define CONFIG_UART2_RTS_PIN -1
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# endif
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#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
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defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
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# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
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#endif
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#define BFIN_UART_TX_FIFO_SIZE 2
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@@ -91,6 +77,7 @@
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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int tx_count;
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@@ -101,23 +88,24 @@ struct bfin_serial_port {
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unsigned int rx_dma_channel;
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struct work_struct tx_dma_workqueue;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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struct timer_list cts_timer;
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int cts_pin;
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int rts_pin;
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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int scts;
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int cts_pin;
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int rts_pin;
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#endif
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};
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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int uart_cts_pin;
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int uart_rts_pin;
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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int uart_cts_pin;
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int uart_rts_pin;
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#endif
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};
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@@ -126,13 +114,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC00400,
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IRQ_UART0_RX,
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IRQ_UART0_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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CONFIG_UART0_CTS_PIN,
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CONFIG_UART0_RTS_PIN,
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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0,
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0,
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#endif
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},
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#endif
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@@ -140,13 +129,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC02000,
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IRQ_UART1_RX,
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IRQ_UART1_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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0,
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0,
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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GPIO_PE10,
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GPIO_PE9,
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#endif
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},
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#endif
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@@ -154,13 +144,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC02100,
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IRQ_UART2_RX,
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IRQ_UART2_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART2_TX,
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CH_UART2_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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CONFIG_UART2_CTS_PIN,
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CONFIG_UART2_RTS_PIN,
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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0,
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0,
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#endif
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},
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#endif
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@@ -168,13 +159,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
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{
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0xFFC03100,
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IRQ_UART3_RX,
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||||
IRQ_UART3_ERROR,
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
CH_UART3_TX,
|
||||
CH_UART3_RX,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||
0,
|
||||
0,
|
||||
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
|
||||
GPIO_PB3,
|
||||
GPIO_PB2,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
|
@@ -53,9 +53,9 @@
|
||||
#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
|
||||
#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
|
||||
|
||||
#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
|
||||
#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
|
||||
#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
|
||||
#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
|
||||
#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
|
||||
#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
|
||||
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
|
||||
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
|
||||
|
||||
@@ -74,6 +74,7 @@
|
||||
struct bfin_serial_port {
|
||||
struct uart_port port;
|
||||
unsigned int old_status;
|
||||
int status_irq;
|
||||
unsigned int lsr;
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
int tx_done;
|
||||
@@ -116,6 +117,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
|
||||
struct bfin_serial_res {
|
||||
unsigned long uart_base_addr;
|
||||
int uart_irq;
|
||||
int uart_status_irq;
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
unsigned int uart_tx_dma_channel;
|
||||
unsigned int uart_rx_dma_channel;
|
||||
@@ -130,6 +132,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
||||
{
|
||||
0xFFC00400,
|
||||
IRQ_UART_RX,
|
||||
IRQ_UART_ERROR,
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
CH_UART_TX,
|
||||
CH_UART_RX,
|
||||
|
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