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ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI

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The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have
specifications to check it) have additional CLKR and FSR pins for McBSP1
receiver. Reset default is that receiver is using bit clock and frame
sync signal from those pins but it is possible to configure to use
also CLKX and FSX pins as well. In fact, other McBSP ports are doing that
internally that transmitter and receiver share the CLKX and FSX.

Add functionaly that machine drivers can set the CLKR and FSR sources by
using the snd_soc_dai_set_sysclk.

Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue.

Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Jarkko Nikula
2009-08-28 15:35:35 +03:00
committed by Mark Brown
parent f4890b5c04
commit d2c0bdaa93
2 changed files with 45 additions and 0 deletions
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4
sound/soc/omap/omap-mcbsp.h
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@@ -32,6 +32,10 @@ enum omap_mcbsp_clksrg_clk {
OMAP_MCBSP_SYSCLK_CLK, /* Internal ICLK */
OMAP_MCBSP_SYSCLK_CLKX_EXT, /* External CLKX pin */
OMAP_MCBSP_SYSCLK_CLKR_EXT, /* External CLKR pin */
OMAP_MCBSP_CLKR_SRC_CLKR, /* CLKR from CLKR pin */
OMAP_MCBSP_CLKR_SRC_CLKX, /* CLKR from CLKX pin */
OMAP_MCBSP_FSR_SRC_FSR, /* FSR from FSR pin */
OMAP_MCBSP_FSR_SRC_FSX, /* FSR from FSX pin */
};
/* McBSP dividers */