drm/radeon/kms: add support for MC/VM setup on SI
Sets up the VM and adds support for the new VM ioctls. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
committed by
Dave Airlie
Dave Airlie
parent
c476dde2ed
commit
d2800ee59e
@@ -1608,3 +1608,331 @@ int si_asic_reset(struct radeon_device *rdev)
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return si_gpu_soft_reset(rdev);
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}
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/* MC */
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static void si_mc_program(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 tmp;
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int i, j;
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/* Initialize HDP */
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for (i = 0, j = 0; i < 32; i++, j += 0x18) {
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WREG32((0x2c14 + j), 0x00000000);
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WREG32((0x2c18 + j), 0x00000000);
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WREG32((0x2c1c + j), 0x00000000);
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WREG32((0x2c20 + j), 0x00000000);
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WREG32((0x2c24 + j), 0x00000000);
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}
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WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
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evergreen_mc_stop(rdev, &save);
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if (radeon_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Lockout access through VGA aperture*/
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WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
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/* Update configuration */
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WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
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rdev->mc.vram_start >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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rdev->mc.vram_end >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
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rdev->vram_scratch.gpu_addr >> 12);
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tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
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tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
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WREG32(MC_VM_FB_LOCATION, tmp);
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/* XXX double check these! */
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WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
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WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
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WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
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WREG32(MC_VM_AGP_BASE, 0);
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WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
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WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
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if (radeon_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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evergreen_mc_resume(rdev, &save);
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/* we need to own VRAM, so turn off the VGA renderer here
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* to stop it overwriting our objects */
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rv515_vga_render_disable(rdev);
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}
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/* SI MC address space is 40 bits */
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static void si_vram_location(struct radeon_device *rdev,
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struct radeon_mc *mc, u64 base)
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{
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mc->vram_start = base;
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if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
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dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
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mc->real_vram_size = mc->aper_size;
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mc->mc_vram_size = mc->aper_size;
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}
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
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{
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u64 size_af, size_bf;
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size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
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size_bf = mc->vram_start & ~mc->gtt_base_align;
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if (size_bf > size_af) {
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if (mc->gtt_size > size_bf) {
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dev_warn(rdev->dev, "limiting GTT\n");
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mc->gtt_size = size_bf;
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}
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mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
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} else {
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if (mc->gtt_size > size_af) {
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dev_warn(rdev->dev, "limiting GTT\n");
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mc->gtt_size = size_af;
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}
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mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
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}
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mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
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dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
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mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
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}
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static void si_vram_gtt_location(struct radeon_device *rdev,
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struct radeon_mc *mc)
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{
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if (mc->mc_vram_size > 0xFFC0000000ULL) {
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/* leave room for at least 1024M GTT */
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dev_warn(rdev->dev, "limiting VRAM\n");
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mc->real_vram_size = 0xFFC0000000ULL;
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mc->mc_vram_size = 0xFFC0000000ULL;
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}
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si_vram_location(rdev, &rdev->mc, 0);
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rdev->mc.gtt_base_align = 0;
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si_gtt_location(rdev, mc);
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}
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static int si_mc_init(struct radeon_device *rdev)
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{
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u32 tmp;
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int chansize, numchan;
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/* Get VRAM informations */
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rdev->mc.vram_is_ddr = true;
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tmp = RREG32(MC_ARB_RAMCFG);
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if (tmp & CHANSIZE_OVERRIDE) {
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chansize = 16;
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} else if (tmp & CHANSIZE_MASK) {
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chansize = 64;
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} else {
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chansize = 32;
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}
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tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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default:
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numchan = 1;
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break;
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case 1:
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numchan = 2;
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break;
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case 2:
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numchan = 4;
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break;
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case 3:
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numchan = 8;
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break;
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case 4:
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numchan = 3;
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break;
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case 5:
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numchan = 6;
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break;
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case 6:
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numchan = 10;
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break;
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case 7:
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numchan = 12;
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break;
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case 8:
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numchan = 16;
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break;
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}
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rdev->mc.vram_width = numchan * chansize;
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/* Could aper size report 0 ? */
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rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
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rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
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/* size in MB on si */
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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si_vram_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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return 0;
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}
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/*
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* GART
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*/
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void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
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{
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/* flush hdp cache */
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WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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/* bits 0-15 are the VM contexts0-15 */
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WREG32(VM_INVALIDATE_REQUEST, 1);
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}
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int si_pcie_gart_enable(struct radeon_device *rdev)
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{
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int r, i;
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if (rdev->gart.robj == NULL) {
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dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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}
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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radeon_gart_restore(rdev);
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/* Setup TLB control */
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WREG32(MC_VM_MX_L1_TLB_CNTL,
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(0xA << 7) |
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ENABLE_L1_TLB |
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SYSTEM_ACCESS_MODE_NOT_IN_SYS |
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ENABLE_ADVANCED_DRIVER_MODEL |
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SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
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ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
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EFFECTIVE_L2_QUEUE_SIZE(7) |
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CONTEXT1_IDENTITY_ACCESS_MODE(1));
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WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
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WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
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L2_CACHE_BIGK_FRAGMENT_SIZE(0));
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/* setup context0 */
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WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
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WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
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WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
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WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
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(u32)(rdev->dummy_page.addr >> 12));
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WREG32(VM_CONTEXT0_CNTL2, 0);
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WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
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WREG32(0x15D4, 0);
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WREG32(0x15D8, 0);
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WREG32(0x15DC, 0);
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/* empty context1-15 */
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/* FIXME start with 1G, once using 2 level pt switch to full
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* vm size space
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*/
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/* set vm size, must be a multiple of 4 */
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WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
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WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE);
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for (i = 1; i < 16; i++) {
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if (i < 8)
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WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
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rdev->gart.table_addr >> 12);
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else
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WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
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rdev->gart.table_addr >> 12);
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}
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/* enable context1-15 */
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WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
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(u32)(rdev->dummy_page.addr >> 12));
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WREG32(VM_CONTEXT1_CNTL2, 0);
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WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
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si_pcie_gart_tlb_flush(rdev);
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DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
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(unsigned)(rdev->mc.gtt_size >> 20),
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(unsigned long long)rdev->gart.table_addr);
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rdev->gart.ready = true;
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return 0;
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}
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void si_pcie_gart_disable(struct radeon_device *rdev)
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{
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/* Disable all tables */
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WREG32(VM_CONTEXT0_CNTL, 0);
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WREG32(VM_CONTEXT1_CNTL, 0);
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/* Setup TLB control */
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WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
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SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
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EFFECTIVE_L2_QUEUE_SIZE(7) |
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CONTEXT1_IDENTITY_ACCESS_MODE(1));
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WREG32(VM_L2_CNTL2, 0);
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WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
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L2_CACHE_BIGK_FRAGMENT_SIZE(0));
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radeon_gart_table_vram_unpin(rdev);
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}
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void si_pcie_gart_fini(struct radeon_device *rdev)
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{
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si_pcie_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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radeon_gart_fini(rdev);
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}
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/*
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* vm
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*/
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int si_vm_init(struct radeon_device *rdev)
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{
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/* number of VMs */
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rdev->vm_manager.nvm = 16;
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/* base offset of vram pages */
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rdev->vm_manager.vram_base_offset = 0;
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return 0;
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}
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void si_vm_fini(struct radeon_device *rdev)
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{
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}
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int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
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{
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if (id < 8)
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WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
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else
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WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
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vm->pt_gpu_addr >> 12);
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/* flush hdp cache */
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WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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/* bits 0-15 are the VM contexts0-15 */
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WREG32(VM_INVALIDATE_REQUEST, 1 << id);
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return 0;
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}
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void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
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{
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if (vm->id < 8)
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WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
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else
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WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
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/* flush hdp cache */
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WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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/* bits 0-15 are the VM contexts0-15 */
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WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
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}
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void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
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{
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if (vm->id == -1)
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return;
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/* flush hdp cache */
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WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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/* bits 0-15 are the VM contexts0-15 */
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WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
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}
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