Merge tag 'arc-4.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: "These are mostly timer/clocksource driver updates which were Reviewed/Acked by Daniel but had to be merged via ARC tree due to dependencies. I will follow up with another pull request with actual ARC changes early next week ! Summary: - Moving ARC timer driver into drivers/clocksource - EZChip timer driver updates [Noam] - ARC AXS103 and HAPS platform updates [Alexey]" * tag 'arc-4.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: axs10x: really enable ARC PGU ARC: rename Zebu platform support to HAPS clocksource: nps: avoid maybe-uninitialized warning clocksource: Add clockevent support to NPS400 driver clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer soc: Support for NPS HW scheduling clocksource: import ARC timer driver ARC: breakout timer include code into separate header ... ARC: move mcip.h into include/soc and adjust the includes ARC: breakout aux handling into a separate header ARC: time: move time_init() out of the driver ARC: timer: gfrc, rtc: build under same option (64-bit timers) ARC: timer: gfrc, rtc: Read BCR to detect whether hardware exists ... ARC: timer: gfrc, rtc: deuglify big endian code
This commit is contained in:
Linus Torvalds
63
include/soc/arc/aux.h
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63
include/soc/arc/aux.h
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/*
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* Copyright (C) 2016-2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __SOC_ARC_AUX_H__
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#define __SOC_ARC_AUX_H__
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#ifdef CONFIG_ARC
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#define read_aux_reg(r) __builtin_arc_lr(r)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r)
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#else /* !CONFIG_ARC */
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static inline int read_aux_reg(u32 r)
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{
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return 0;
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}
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/*
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* function helps elide unused variable warning
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* see: http://lists.infradead.org/pipermail/linux-snps-arc/2016-November/001748.html
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*/
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static inline void write_aux_reg(u32 r, u32 v)
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{
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;
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}
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#endif
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#define READ_BCR(reg, into) \
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{ \
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unsigned int tmp; \
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tmp = read_aux_reg(reg); \
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if (sizeof(tmp) == sizeof(into)) { \
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into = *((typeof(into) *)&tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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#define WRITE_AUX(reg, into) \
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{ \
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unsigned int tmp; \
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if (sizeof(tmp) == sizeof(into)) { \
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tmp = (*(unsigned int *)&(into)); \
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write_aux_reg(reg, tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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#endif
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103
include/soc/arc/mcip.h
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103
include/soc/arc/mcip.h
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/*
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* ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
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*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SOC_ARC_MCIP_H
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#define __SOC_ARC_MCIP_H
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#include <soc/arc/aux.h>
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#define ARC_REG_MCIP_BCR 0x0d0
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#define ARC_REG_MCIP_CMD 0x600
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#define ARC_REG_MCIP_WDATA 0x601
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#define ARC_REG_MCIP_READBACK 0x602
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struct mcip_cmd {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, param:16, cmd:8;
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#else
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unsigned int cmd:8, param:16, pad:8;
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#endif
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#define CMD_INTRPT_GENERATE_IRQ 0x01
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#define CMD_INTRPT_GENERATE_ACK 0x02
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#define CMD_INTRPT_READ_STATUS 0x03
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#define CMD_INTRPT_CHECK_SOURCE 0x04
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/* Semaphore Commands */
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#define CMD_SEMA_CLAIM_AND_READ 0x11
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#define CMD_SEMA_RELEASE 0x12
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#define CMD_DEBUG_SET_MASK 0x34
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#define CMD_DEBUG_SET_SELECT 0x36
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#define CMD_GFRC_READ_LO 0x42
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#define CMD_GFRC_READ_HI 0x43
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#define CMD_IDU_ENABLE 0x71
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#define CMD_IDU_DISABLE 0x72
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#define CMD_IDU_SET_MODE 0x74
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#define CMD_IDU_SET_DEST 0x76
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#define CMD_IDU_SET_MASK 0x7C
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#define IDU_M_TRIG_LEVEL 0x0
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#define IDU_M_TRIG_EDGE 0x1
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#define IDU_M_DISTRI_RR 0x0
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#define IDU_M_DISTRI_DEST 0x2
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};
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struct mcip_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:8,
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idu:1, llm:1, num_cores:6,
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iocoh:1, gfrc:1, dbg:1, pad2:1,
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msg:1, sem:1, ipi:1, pad:1,
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ver:8;
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#else
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unsigned int ver:8,
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pad:1, ipi:1, sem:1, msg:1,
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pad2:1, dbg:1, gfrc:1, iocoh:1,
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num_cores:6, llm:1, idu:1,
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pad3:8;
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#endif
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};
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/*
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* MCIP programming model
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*
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* - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
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* (param could be irq, common_irq, core_id ...)
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* - More involved commands setup MCIP_WDATA with cmd specific data
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* before invoking the simple command
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*/
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static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
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{
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struct mcip_cmd buf;
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buf.pad = 0;
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buf.cmd = cmd;
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buf.param = param;
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WRITE_AUX(ARC_REG_MCIP_CMD, buf);
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}
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/*
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* Setup additional data for a cmd
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* Callers need to lock to ensure atomicity
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*/
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static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
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unsigned int data)
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{
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write_aux_reg(ARC_REG_MCIP_WDATA, data);
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__mcip_cmd(cmd, param);
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}
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#endif
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38
include/soc/arc/timers.h
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38
include/soc/arc/timers.h
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@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SOC_ARC_TIMERS_H
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#define __SOC_ARC_TIMERS_H
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#include <soc/arc/aux.h>
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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/* CTRL reg bits */
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#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMERN_MAX 0xFFFFFFFF
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#define ARC_REG_TIMERS_BCR 0x75
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struct bcr_timer {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
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#else
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unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
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#endif
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};
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#endif
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59
include/soc/nps/mtm.h
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59
include/soc/nps/mtm.h
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@@ -0,0 +1,59 @@
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/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef SOC_NPS_MTM_H
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#define SOC_NPS_MTM_H
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#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
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#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
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static inline void hw_schd_save(unsigned int *flags)
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{
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__asm__ __volatile__(
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" .word %1\n"
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" st r3,[%0]\n"
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:
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: "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
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: "r3", "memory");
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}
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static inline void hw_schd_restore(unsigned int flags)
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{
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__asm__ __volatile__(
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" mov r3, %0\n"
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" .word %1\n"
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:
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: "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
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: "r3");
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}
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#endif /* SOC_NPS_MTM_H */
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