Merge tag 'arc-4.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: "These are mostly timer/clocksource driver updates which were Reviewed/Acked by Daniel but had to be merged via ARC tree due to dependencies. I will follow up with another pull request with actual ARC changes early next week ! Summary: - Moving ARC timer driver into drivers/clocksource - EZChip timer driver updates [Noam] - ARC AXS103 and HAPS platform updates [Alexey]" * tag 'arc-4.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: axs10x: really enable ARC PGU ARC: rename Zebu platform support to HAPS clocksource: nps: avoid maybe-uninitialized warning clocksource: Add clockevent support to NPS400 driver clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer soc: Support for NPS HW scheduling clocksource: import ARC timer driver ARC: breakout timer include code into separate header ... ARC: move mcip.h into include/soc and adjust the includes ARC: breakout aux handling into a separate header ARC: time: move time_init() out of the driver ARC: timer: gfrc, rtc: build under same option (64-bit timers) ARC: timer: gfrc, rtc: Read BCR to detect whether hardware exists ... ARC: timer: gfrc, rtc: deuglify big endian code
This commit is contained in:
Linus Torvalds
@@ -20,7 +20,6 @@
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#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
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#define ARC_REG_SLC_BCR 0xce
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#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
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#define ARC_REG_TIMERS_BCR 0x75
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#define ARC_REG_AP_BCR 0x76
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#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
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#define ARC_REG_XY_MEM_BCR 0x79
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@@ -112,90 +111,7 @@
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#ifndef __ASSEMBLY__
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/*
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******************************************************************
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* Inline ASM macros to read/write AUX Regs
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* Essentially invocation of lr/sr insns from "C"
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*/
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#if 1
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(reg_immed, val) \
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__builtin_arc_sr((unsigned int)(val), reg_immed)
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#else
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#define read_aux_reg(reg) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__( \
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" lr %0, [%1]" \
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: "=r"(__ret) \
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: "i"(reg)); \
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__ret; \
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})
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/*
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* Aux Reg address is specified as long immediate by caller
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* e.g.
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* write_aux_reg(0x69, some_val);
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* This generates tightest code.
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*/
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#define write_aux_reg(reg_imm, val) \
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({ \
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__asm__ __volatile__( \
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" sr %0, [%1] \n" \
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: \
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: "ir"(val), "i"(reg_imm)); \
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})
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/*
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* Aux Reg address is specified in a variable
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* * e.g.
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* reg_num = 0x69
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* write_aux_reg2(reg_num, some_val);
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* This has to generate glue code to load the reg num from
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* memory to a reg hence not recommended.
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*/
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#define write_aux_reg2(reg_in_var, val) \
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({ \
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unsigned int tmp; \
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\
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__asm__ __volatile__( \
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" ld %0, [%2] \n\t" \
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" sr %1, [%0] \n\t" \
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: "=&r"(tmp) \
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: "r"(val), "memory"(®_in_var)); \
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})
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#endif
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#define READ_BCR(reg, into) \
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{ \
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unsigned int tmp; \
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tmp = read_aux_reg(reg); \
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if (sizeof(tmp) == sizeof(into)) { \
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into = *((typeof(into) *)&tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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#define WRITE_AUX(reg, into) \
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{ \
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unsigned int tmp; \
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if (sizeof(tmp) == sizeof(into)) { \
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tmp = (*(unsigned int *)&(into)); \
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write_aux_reg(reg, tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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#include <soc/arc/aux.h>
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/* Helpers */
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#define TO_KB(bytes) ((bytes) >> 10)
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@@ -291,13 +207,7 @@ struct bcr_fp_arcv2 {
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#endif
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};
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struct bcr_timer {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
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#else
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unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
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#endif
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};
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#include <soc/arc/timers.h>
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struct bcr_bpu_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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@@ -1,107 +0,0 @@
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/*
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* ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
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*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_MCIP_H
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#define __ASM_MCIP_H
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#ifdef CONFIG_ISA_ARCV2
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#include <asm/arcregs.h>
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#define ARC_REG_MCIP_BCR 0x0d0
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#define ARC_REG_MCIP_CMD 0x600
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#define ARC_REG_MCIP_WDATA 0x601
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#define ARC_REG_MCIP_READBACK 0x602
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struct mcip_cmd {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, param:16, cmd:8;
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#else
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unsigned int cmd:8, param:16, pad:8;
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#endif
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#define CMD_INTRPT_GENERATE_IRQ 0x01
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#define CMD_INTRPT_GENERATE_ACK 0x02
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#define CMD_INTRPT_READ_STATUS 0x03
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#define CMD_INTRPT_CHECK_SOURCE 0x04
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/* Semaphore Commands */
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#define CMD_SEMA_CLAIM_AND_READ 0x11
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#define CMD_SEMA_RELEASE 0x12
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#define CMD_DEBUG_SET_MASK 0x34
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#define CMD_DEBUG_SET_SELECT 0x36
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#define CMD_GFRC_READ_LO 0x42
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#define CMD_GFRC_READ_HI 0x43
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#define CMD_IDU_ENABLE 0x71
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#define CMD_IDU_DISABLE 0x72
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#define CMD_IDU_SET_MODE 0x74
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#define CMD_IDU_SET_DEST 0x76
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#define CMD_IDU_SET_MASK 0x7C
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#define IDU_M_TRIG_LEVEL 0x0
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#define IDU_M_TRIG_EDGE 0x1
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#define IDU_M_DISTRI_RR 0x0
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#define IDU_M_DISTRI_DEST 0x2
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};
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struct mcip_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:8,
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idu:1, llm:1, num_cores:6,
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iocoh:1, gfrc:1, dbg:1, pad2:1,
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msg:1, sem:1, ipi:1, pad:1,
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ver:8;
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#else
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unsigned int ver:8,
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pad:1, ipi:1, sem:1, msg:1,
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pad2:1, dbg:1, gfrc:1, iocoh:1,
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num_cores:6, llm:1, idu:1,
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pad3:8;
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#endif
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};
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/*
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* MCIP programming model
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*
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* - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
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* (param could be irq, common_irq, core_id ...)
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* - More involved commands setup MCIP_WDATA with cmd specific data
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* before invoking the simple command
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*/
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static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
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{
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struct mcip_cmd buf;
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buf.pad = 0;
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buf.cmd = cmd;
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buf.param = param;
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WRITE_AUX(ARC_REG_MCIP_CMD, buf);
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}
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/*
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* Setup additional data for a cmd
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* Callers need to lock to ensure atomicity
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*/
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static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
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unsigned int data)
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{
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write_aux_reg(ARC_REG_MCIP_WDATA, data);
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__mcip_cmd(cmd, param);
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}
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#endif
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#endif
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