crypto: caam - add register map changes cf. Era 10
Era 10 changes the register map. The updates that affect the drivers: -new version registers are added -DBG_DBG[deco_state] field is moved to a new register - DBG_EXEC[19:16] @ 8_0E3Ch. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@@ -3,6 +3,7 @@
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* caam - Freescale FSL CAAM support for ahash functions of crypto API
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*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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* Based on caamalg.c crypto API driver.
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*
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@@ -1801,7 +1802,7 @@ static int __init caam_algapi_hash_init(void)
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int i = 0, err = 0;
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struct caam_drv_private *priv;
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unsigned int md_limit = SHA512_DIGEST_SIZE;
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u32 cha_inst, cha_vid;
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u32 md_inst, md_vid;
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dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
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if (!dev_node) {
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@@ -1831,18 +1832,27 @@ static int __init caam_algapi_hash_init(void)
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* Register crypto algorithms the device supports. First, identify
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* presence and attributes of MD block.
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*/
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cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
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cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
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if (priv->era < 10) {
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md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) &
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CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
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md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
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CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
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} else {
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u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha);
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md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
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md_inst = mdha & CHA_VER_NUM_MASK;
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}
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/*
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* Skip registration of any hashing algorithms if MD block
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* is not present.
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*/
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if (!((cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT))
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if (!md_inst)
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return -ENODEV;
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/* Limit digest size based on LP256 */
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if ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256)
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if (md_vid == CHA_VER_VID_MD_LP256)
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md_limit = SHA256_DIGEST_SIZE;
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INIT_LIST_HEAD(&hash_list);
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