Merge branch 'pci/host-tegra' into next
* pci/host-tegra: PCI: tegra: Add Tegra186 PCIe support dt-bindings: pci: tegra: Document Tegra186 PCIe DT PCI: tegra: Use generic accessors where possible
This commit is contained in:
Bjorn Helgaas
@@ -1,10 +1,15 @@
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NVIDIA Tegra PCIe controller
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Required properties:
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- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
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"nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
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Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
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<chip> is tegra132 or tegra210.
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- compatible: Must be:
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- "nvidia,tegra20-pcie": for Tegra20
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- "nvidia,tegra30-pcie": for Tegra30
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- "nvidia,tegra124-pcie": for Tegra124 and Tegra132
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- "nvidia,tegra210-pcie": for Tegra210
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- "nvidia,tegra186-pcie": for Tegra186
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- power-domains: To ungate power partition by BPMP powergate driver. Must
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contain BPMP phandle and PCIe power partition ID. This is required only
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for Tegra186.
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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@@ -124,6 +129,16 @@ Power supplies for Tegra210:
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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Power supplies for Tegra186:
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- Required:
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- dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
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supply 1.8 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 1.8 V.
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- vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
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supply 1.8 V.
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Root ports are defined as subnodes of the PCIe controller node.
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Required properties:
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@@ -546,3 +561,114 @@ Board DTS:
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status = "okay";
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};
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};
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Tegra186:
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---------
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SoC DTSI:
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pcie@10003000 {
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compatible = "nvidia,tegra186-pcie";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
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device_type = "pci";
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reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
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0x0 0x10003800 0x0 0x00000800 /* AFI registers */
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0x0 0x40000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
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0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
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clocks = <&bpmp TEGRA186_CLK_AFI>,
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<&bpmp TEGRA186_CLK_PCIE>,
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<&bpmp TEGRA186_CLK_PLLE>;
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clock-names = "afi", "pex", "pll_e";
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resets = <&bpmp TEGRA186_RESET_AFI>,
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<&bpmp TEGRA186_RESET_PCIE>,
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<&bpmp TEGRA186_RESET_PCIEXCLK>;
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reset-names = "afi", "pex", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie@10003000 {
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status = "okay";
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dvdd-pex-supply = <&vdd_pex>;
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hvdd-pex-pll-supply = <&vdd_1v8>;
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hvdd-pex-supply = <&vdd_1v8>;
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vddio-pexctl-aud-supply = <&vdd_1v8>;
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pci@1,0 {
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nvidia,num-lanes = <4>;
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status = "okay";
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};
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pci@2,0 {
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nvidia,num-lanes = <0>;
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status = "disabled";
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};
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pci@3,0 {
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nvidia,num-lanes = <1>;
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status = "disabled";
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};
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};
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