Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"MIPS updates:
- All the things that didn't make 3.10.
- Removes the Windriver PPMC platform. Nobody will miss it.
- Remove a workaround from kernel/irq/irqdomain.c which was there
exclusivly for MIPS. Patch by Grant Likely.
- More small improvments for the SEAD 3 platform
- Improvments on the BMIPS / SMP support for the BCM63xx series.
- Various cleanups of dead leftovers.
- Platform support for the Cavium Octeon-based EdgeRouter Lite.
Two large KVM patchsets didn't make it for this pull request because
their respective authors are vacationing"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (124 commits)
MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER
MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions
MIPS: SEAD3: Disable L2 cache on SEAD-3.
MIPS: BCM63xx: Enable second core SMP on BCM6328 if available
MIPS: BCM63xx: Add SMP support to prom.c
MIPS: define write{b,w,l,q}_relaxed
MIPS: Expose missing pci_io{map,unmap} declarations
MIPS: Malta: Update GCMP detection.
Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"
MIPS: APSP: Remove <asm/kspd.h>
SSB: Kconfig: Amend SSB_EMBEDDED dependencies
MIPS: microMIPS: Fix improper definition of ISA exception bit.
MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.
MIPS: Declare emulate_load_store_microMIPS as a static function.
MIPS: Fix typos and cleanup comment
MIPS: Cleanup indentation and whitespace
MIPS: BMIPS: support booting from physical CPU other than 0
MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS
MIPS: GIC: Fix gic_set_affinity infinite loop
MIPS: Don't save/restore OCTEON wide multiplier state on syscalls.
...
This commit is contained in:
Linus Torvalds
@@ -9,6 +9,7 @@
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* compile time if only one CPU support is enabled (idea stolen from
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* arm mach-types)
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*/
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#define BCM3368_CPU_ID 0x3368
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#define BCM6328_CPU_ID 0x6328
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
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u8 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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#ifdef CONFIG_BCM63XX_CPU_3368
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
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# endif
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# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
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#else
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# define BCMCPU_IS_3368() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6328
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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@@ -193,6 +207,53 @@ enum bcm63xx_regs_set {
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#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
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#define RSET_RNG_SIZE 20
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/*
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* 3368 register sets base address
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*/
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#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
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#define BCM_3368_PERF_BASE (0xfff8c000)
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#define BCM_3368_TIMER_BASE (0xfff8c040)
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#define BCM_3368_WDT_BASE (0xfff8c080)
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#define BCM_3368_UART0_BASE (0xfff8c100)
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#define BCM_3368_UART1_BASE (0xfff8c120)
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#define BCM_3368_GPIO_BASE (0xfff8c080)
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#define BCM_3368_SPI_BASE (0xfff8c800)
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#define BCM_3368_HSSPI_BASE (0xdeadbeef)
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#define BCM_3368_UDC0_BASE (0xdeadbeef)
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#define BCM_3368_USBDMA_BASE (0xdeadbeef)
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#define BCM_3368_OHCI0_BASE (0xdeadbeef)
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#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_3368_USBD_BASE (0xdeadbeef)
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#define BCM_3368_MPI_BASE (0xfff80000)
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#define BCM_3368_PCMCIA_BASE (0xfff80054)
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#define BCM_3368_PCIE_BASE (0xdeadbeef)
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#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_3368_DSL_BASE (0xdeadbeef)
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#define BCM_3368_UBUS_BASE (0xdeadbeef)
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#define BCM_3368_ENET0_BASE (0xfff98000)
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#define BCM_3368_ENET1_BASE (0xfff98800)
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#define BCM_3368_ENETDMA_BASE (0xfff99800)
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#define BCM_3368_ENETDMAC_BASE (0xfff99900)
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#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
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#define BCM_3368_ENETSW_BASE (0xdeadbeef)
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#define BCM_3368_EHCI0_BASE (0xdeadbeef)
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#define BCM_3368_SDRAM_BASE (0xdeadbeef)
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#define BCM_3368_MEMC_BASE (0xfff84000)
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#define BCM_3368_DDR_BASE (0xdeadbeef)
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#define BCM_3368_M2M_BASE (0xdeadbeef)
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#define BCM_3368_ATM_BASE (0xdeadbeef)
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#define BCM_3368_XTM_BASE (0xdeadbeef)
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#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
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#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_3368_PCM_BASE (0xfff9c200)
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#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
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#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_3368_RNG_BASE (0xdeadbeef)
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#define BCM_3368_MISC_BASE (0xdeadbeef)
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/*
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* 6328 register sets base address
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*/
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@@ -238,6 +299,8 @@ enum bcm63xx_regs_set {
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#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_RNG_BASE (0xdeadbeef)
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#define BCM_6328_MISC_BASE (0xb0001800)
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#define BCM_6328_OTP_BASE (0xb0000600)
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/*
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* 6338 register sets base address
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*/
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@@ -623,6 +686,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_base[set];
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#else
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#ifdef CONFIG_BCM63XX_CPU_3368
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__GEN_RSET(3368)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6328
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__GEN_RSET(6328)
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#endif
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@@ -689,6 +755,52 @@ enum bcm63xx_irq {
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IRQ_XTM_DMA0,
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};
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/*
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* 3368 irqs
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*/
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#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
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#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
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#define BCM_3368_DSL_IRQ 0
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#define BCM_3368_UDC0_IRQ 0
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#define BCM_3368_OHCI0_IRQ 0
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#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
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#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
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#define BCM_3368_HSSPI_IRQ 0
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#define BCM_3368_EHCI0_IRQ 0
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#define BCM_3368_USBD_IRQ 0
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#define BCM_3368_USBD_RXDMA0_IRQ 0
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#define BCM_3368_USBD_TXDMA0_IRQ 0
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#define BCM_3368_USBD_RXDMA1_IRQ 0
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#define BCM_3368_USBD_TXDMA1_IRQ 0
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#define BCM_3368_USBD_RXDMA2_IRQ 0
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#define BCM_3368_USBD_TXDMA2_IRQ 0
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#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
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#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
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#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
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#define BCM_3368_PCMCIA_IRQ 0
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#define BCM_3368_ATM_IRQ 0
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#define BCM_3368_ENETSW_RXDMA0_IRQ 0
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#define BCM_3368_ENETSW_RXDMA1_IRQ 0
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#define BCM_3368_ENETSW_RXDMA2_IRQ 0
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#define BCM_3368_ENETSW_RXDMA3_IRQ 0
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#define BCM_3368_ENETSW_TXDMA0_IRQ 0
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#define BCM_3368_ENETSW_TXDMA1_IRQ 0
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#define BCM_3368_ENETSW_TXDMA2_IRQ 0
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#define BCM_3368_ENETSW_TXDMA3_IRQ 0
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#define BCM_3368_XTM_IRQ 0
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#define BCM_3368_XTM_DMA0_IRQ 0
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#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
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#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
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#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
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#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
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/*
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* 6328 irqs
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*/
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@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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return 32;
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case BCM3368_CPU_ID:
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case BCM6358_CPU_ID:
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return 40;
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case BCM6338_CPU_ID:
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@@ -15,6 +15,39 @@
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/* Clock Control register */
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#define PERF_CKCTL_REG 0x4
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#define CKCTL_3368_MAC_EN (1 << 3)
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#define CKCTL_3368_TC_EN (1 << 5)
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#define CKCTL_3368_US_TOP_EN (1 << 6)
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#define CKCTL_3368_DS_TOP_EN (1 << 7)
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#define CKCTL_3368_APM_EN (1 << 8)
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#define CKCTL_3368_SPI_EN (1 << 9)
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#define CKCTL_3368_USBS_EN (1 << 10)
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#define CKCTL_3368_BMU_EN (1 << 11)
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#define CKCTL_3368_PCM_EN (1 << 12)
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#define CKCTL_3368_NTP_EN (1 << 13)
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#define CKCTL_3368_ACP_B_EN (1 << 14)
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#define CKCTL_3368_ACP_A_EN (1 << 15)
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#define CKCTL_3368_EMUSB_EN (1 << 17)
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#define CKCTL_3368_ENET0_EN (1 << 18)
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#define CKCTL_3368_ENET1_EN (1 << 19)
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#define CKCTL_3368_USBU_EN (1 << 20)
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#define CKCTL_3368_EPHY_EN (1 << 21)
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#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
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CKCTL_3368_TC_EN | \
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CKCTL_3368_US_TOP_EN | \
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CKCTL_3368_DS_TOP_EN | \
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CKCTL_3368_APM_EN | \
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CKCTL_3368_SPI_EN | \
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CKCTL_3368_USBS_EN | \
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CKCTL_3368_BMU_EN | \
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CKCTL_3368_PCM_EN | \
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CKCTL_3368_NTP_EN | \
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CKCTL_3368_ACP_B_EN | \
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CKCTL_3368_ACP_A_EN | \
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CKCTL_3368_EMUSB_EN | \
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CKCTL_3368_USBU_EN)
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#define CKCTL_6328_PHYMIPS_EN (1 << 0)
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#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
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#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
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@@ -181,6 +214,7 @@
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#define SYS_PLL_SOFT_RESET 0x1
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/* Interrupt Mask register */
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#define PERF_IRQMASK_3368_REG 0xc
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#define PERF_IRQMASK_6328_REG 0x20
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#define PERF_IRQMASK_6338_REG 0xc
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#define PERF_IRQMASK_6345_REG 0xc
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@@ -190,6 +224,7 @@
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#define PERF_IRQMASK_6368_REG 0x20
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/* Interrupt Status register */
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#define PERF_IRQSTAT_3368_REG 0x10
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#define PERF_IRQSTAT_6328_REG 0x28
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#define PERF_IRQSTAT_6338_REG 0x10
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#define PERF_IRQSTAT_6345_REG 0x10
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@@ -199,6 +234,7 @@
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#define PERF_IRQSTAT_6368_REG 0x28
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/* External Interrupt Configuration register */
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#define PERF_EXTIRQ_CFG_REG_3368 0x14
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#define PERF_EXTIRQ_CFG_REG_6328 0x18
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#define PERF_EXTIRQ_CFG_REG_6338 0x14
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#define PERF_EXTIRQ_CFG_REG_6345 0x14
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@@ -236,6 +272,13 @@
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#define PERF_SOFTRESET_6362_REG 0x10
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#define PERF_SOFTRESET_6368_REG 0x10
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#define SOFTRESET_3368_SPI_MASK (1 << 0)
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#define SOFTRESET_3368_ENET_MASK (1 << 2)
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#define SOFTRESET_3368_MPI_MASK (1 << 3)
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#define SOFTRESET_3368_EPHY_MASK (1 << 6)
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#define SOFTRESET_3368_USBS_MASK (1 << 11)
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#define SOFTRESET_3368_PCM_MASK (1 << 13)
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#define SOFTRESET_6328_SPI_MASK (1 << 0)
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#define SOFTRESET_6328_EPHY_MASK (1 << 1)
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#define SOFTRESET_6328_SAR_MASK (1 << 2)
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@@ -1370,7 +1413,7 @@
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#define SPI_6348_RX_DATA 0x80
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#define SPI_6348_RX_DATA_SIZE 0x3f
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/* BCM 6358/6262/6368 SPI core */
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/* BCM 3368/6358/6262/6368 SPI core */
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#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
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#define SPI_6358_MSG_CTL_WIDTH 16
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#define SPI_6358_MSG_DATA 0x02
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@@ -1511,4 +1554,11 @@
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#define PCIE_DEVICE_OFFSET 0x8000
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/*************************************************************************
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* _REG relative to RSET_OTP
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*************************************************************************/
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#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
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#define OTP_6328_REG3_TP1_DISABLED BIT(9)
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#endif /* BCM63XX_REGS_H_ */
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@@ -47,6 +47,12 @@ struct board_info {
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/* GPIO LEDs */
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struct gpio_led leds[5];
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/* External PHY reset GPIO */
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unsigned int ephy_reset_gpio;
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/* External PHY reset GPIO flags from gpio.h */
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unsigned long ephy_reset_gpio_flags;
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};
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#endif /* ! BOARD_BCM963XX_H_ */
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@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
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static inline int is_bcm63xx_internal_registers(phys_t offset)
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{
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switch (bcm63xx_get_cpu_id()) {
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case BCM3368_CPU_ID:
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if (offset >= 0xfff80000)
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return 1;
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break;
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case BCM6338_CPU_ID:
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case BCM6345_CPU_ID:
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case BCM6348_CPU_ID:
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Block a user